10:57 <apritzel> Does anyone have some info on the T113/R528 CPU control registers? The manual describes the reset bits, but no power clamps or power switches, although they are shown on a diagram

12:33 <daschaos> apritzel: in what diagram did you found it?

12:54 <apritzel> daschaos: in the T113s user manual, Figure 3-1: "Default Power Domain of Cluster0". There is a "PWR_SW" for each core, and the description below that mentions them as well

13:24 <daschaos> apritzel: This is only a guess, but i think you can trigger that switches with: nCOREPORESET and DBGPWRUPREQ. But not directly. I looked at the documentation for the Cortex A7: https://developer.arm.com/documentation/ddi0464/f/

13:24 <daschaos> Maybe that is helping

13:26 <apritzel> yeah, correlating that to the TRM power up/down sequence was next on my list. I guess we can get away with just playing with the reset line for now, but the U-Boot PSCI code for the other SoCs does more than that

13:38 <apritzel> daschaos: and which signals/registers are you referring to, exactly? There is C_DBGPWRUPREQ in the T113 manual, which is r/o and just reports the state of the line that an *external debugger* would assert

13:45 <daschaos> Yeah, i didn't saw that the register is read only in the t113 docs