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<macromorgan>
looks like we have bootm in the U-Boot image, and if it fails to boot it will take my commands over serial.
<macromorgan>
good news too is it looks like I can directly poke at the RAM registers from U-Boot
<macromorgan>
so TL;DR if I take away anything that's bootable then U-Boot will let me interact with it
<macromorgan>
I'm going to start work on a very simple device tree and see if I can get it to boot at all
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<junari>
So T507 phy_init variant is compatible with H700
<junari>
In the AW bootloader, one or another variant is selected based on the one register (SID maybe? I don't remember). I think in the mainline u-boot should be something similar
<junari>
I’m currently on a pause on the project with t507, only in a few months will I be able to work on this in more detail
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<jernej>
junari, apritzel: libdram check value of 0x3006200 and then selects appropriate phy_init array
<jernej>
I guess having 2 arrays per DRAM type isn't that bad for SPL size?
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<apritzel>
jernej: for the H616 the SPL size is not critical. So 0x3006200 is the SID base, so is that the same value we check already ("die revision"), for the RVBAR register location?
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<jernej>
where can I find this code?
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<apritzel>
ah, no, we use a different register for that (in the "SRAM controller", at 0x3000024)
<apritzel>
but we use some SID registers already in the D1/T113-s3 DRAM code, look for SUNXI_SID_BASE in drivers/ram/sunxi/dram_sun20i_d1.c
<apritzel>
I think the first word of the SID is the one we also use for the bin detection in the cpufreq code
<jernej>
although I think speedgrade isn't proper name
<jernej>
or maybe it could be only a part of it, so masks are used in code I linked before
<apritzel>
it's probably a bin or batch number, and in the context of the cpufreq that translates to "speed grades". The name might even come from BSP code?
<jernej>
I still think this number is mostly chip dependent, like all H616 will have 0x2000 or similar, but not 0x6c00, which seems to be used on T507