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<wingrime-ww> apritzel: do you already know how enter secure?
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<wingrime-ww> may-be it is incorrect
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<jernej> apritzel: fyi, just noticed that boot0 sets different voltage for different variants of sun50iw9 die. For some is 940 mV and for some is 960 mV.
<jernej> and another interesting tidbit. Based on SID value, boot0 might power down two cores.
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<apritzel> jernej: that's for the CPU voltage at boot time, and the frequency is then 1008 MHz?
<apritzel> that would match the OPP for that speed, which has 940mV for one speed bin, and 950mV for the others
<apritzel> though I don't get why they just don't program 960mV everywhere, surely the 20mV more don't matter at this point, as cpufreq is about to kick in seconds later anyway
<jernej> yeah, that would be easier
<apritzel> wingrime-ww: if you boot from SD card, the code is running in secure SVC. If you enter FEL via the branch from there, then the code loaded via FEL is executed in non-secure, and the SMC doesn't change that.
<apritzel> That is at least what I figured. I don't know if that's different if you enter FEL via another way (FEL button, or no boot media)
<apritzel> I haven't opened the tablet, but there is possibly a FEL pad on the PCB. And for sabotaging the eMMC I would rather have a plan B first, for instance mainline U-Boot running
<jernej> apritzel: Regarding DRAM init issues on other than H616/H313 SoCs, what do you say about this patch? http://sprunge.us/xdifqT
<apritzel> it's not a real showstopper, as you can just boot from SD every time, but it's of course tedious in the early phase
<apritzel> jernej: do we actually need runtime detection? Can't this be selected at build time?
<apritzel> but in general if that helps: of course
<jernej> well, you would need to make distinction between T507 and H616, for example
<jernej> there is none yet
<jernej> of course this can be Kconfig option, but runtime detection, as done in BSP, is more future proof
<jernej> since we don't know exactly all possible combinations
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<wingrime-ww> are BSP for A523 avaliable somewhere ?
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<jernej> apritzel: H616 DRAM type selection should be choice, right? Only one can be used anyway. I can also make that patch.
<jernej> eh, it is already
<jernej> missed keyword
<apritzel> wingrime-ww: if you do a github code search for "sun55iw3", you will find some Linux repos
<apritzel> wingrime-ww: I put a link to that and the user manual into the Wiki
<jernej> has anyone found axp858 datasheet?
<apritzel> jernej: do you have further information? How many DC/DCs, how many LDOs, battery charger or not? Maybe it's yet again just an alias for another chip?
<jernej> 6x dcdc, 5x aldo, 5x bldo, 4x cldo, special ldo, sw, pek and i2c address 0x36
<jernej> if BSP DT is to be trusted
<jernej> I've seen pdf on Chinese forums, but I can't download from them
<jernej> looks very similar to axp15060 based on output counts and i2c address
<apritzel> does the BSP contain any *code* for that PMIC? maybe you can fish the register offsets and voltage ranges from there, and be it for further comparisons?
<apritzel> I found some AXP2202 values somewhere, and could confirm that they were the same as the AXP717
<junari> jernej: i think that axp858 is the same as axp853t that comes together with t507
<jernej> apritzel: I did, and everything I compared looks the same
<wingrime-ww> who knows what is diffrent between D1 and D1-H ?
<apritzel> wingrime-ww: Allwinner lately relabelled all SoCs to have a "-H" appended when they provide a HDMI output, might be licensing related
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<jernej> ah, axp15060 is already supported since last year in linux, so I guess axp858 can piggy back on that
<apritzel> jernej: a new device you are looking at?
<apritzel> I mean board
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<ity> apritzel: ah, and which devices does devfreq handle? And, I guess I will need to look into how CPU frequency scaling works as well haha.
<apritzel> ity: in the A64 case it's the DRAM controller, it allows to clock that down, to save power
<ity> OOOH, interesting. Is that documented in the datasheet/manual?
<apritzel> the manual is pretty thin on those things, but it documents the MBUS and DRAM controller clocks at least
<apritzel> the commit message might give you some idea
<apritzel> (not sure what you are after beyond that, though)
<ity> Hmm, I see, so I should read the commit messages for sun8i_a33_mbus ? Why is the driver called mbus when it handles devfreq btw
<ity> My goal is to document as much about the device as I can