<neggles>
Grommish: octeon, octeonplus are soft-float, octeon II might be? octeon III has an FPU
<Grommish>
neggles: Octeon3 can handle soft-float?
<neggles>
anything that has an FPU can run without FPU instructions
<neggles>
just 'cause it's there doesn't mean you have to use it :P raspbian ran softfloat on Pi 2 for quite a while even though the core had an FPU
<Grommish>
neggles: Ok. I think I got a lead on the SIGILL issues I've been having.. Apparently, rust requires +soft-float to be passed in the definition, even if -msoft-float is passed :/
<neggles>
ha! that'd do it
<neggles>
I don't know if octeon II has an FPU, but I can find out :D
<Grommish>
Since it's all lumped under mips64/octeon for Openwrt, I'll just set soft-float for everything
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<neggles>
IMO octeon needs to be split into two targets, probably octeon and octeon3 - the CN7xxx chips are in a *lot* of hardware that's starting to make its way onto the used market, and they have significantly fewer weird/annoying hardware glitches to deal with
<neggles>
if it were up to me, I'd drop support for everything below CN6xxx in future releases
<neggles>
it is time to let the ERLite-3 die, it wasn't good even when it was new >.>
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<Grommish>
neggles: No doubt, and I agree.. I've got the CN7020 and Octeon+ targeting, but since the -march=octeon3 doesn't fix the mem leak, I dunno if it matters
<Grommish>
If it did, then it would be a no-brainer :D
<neggles>
Grommish: there is a lot of code that is #ifdef'd out with a kernel configured for octeon 3 though, not just the arch flag
<neggles>
including a bunch of buggy hacky code for the ethernet interfaces on pre-CN7000 iirc (though i might be thinking of the half-finished nand controller code)
<Grommish>
neggles: *nod* I had initially looked at it early on but after the door shut on spliting the target, I never looked further
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<f00b4r0>
Grommish: oh that one is a keeper ;D
<neggles>
hah
<neggles>
if it ain't broke, don't fix it
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<rsalvaterra>
You guys have it backwards. If it's not broken, break it so you can fix it. ;)
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<Grommish>
rsalvaterra: That's for hardware mods..
<Grommish>
rsalvaterra: Cars, electronics, buildings.. If it ain't broke, you aren't fixing it right
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<aiyion>
Need some experience of you guys: using my ch341a to read an spi flash I'm reading gibberish, while the chips is still part of the board. I know it's not meant to work like that, but happened to with a lot of devices I used before.
<aiyion>
apparently this is the first one I encounter, where I can not read the chips contents while its soldered in place.
<aiyion>
Are there any tricks I might try before desoldering the chip?
<aiyion>
I'd really like to avoid that.
<Habbie>
somebody in here mentioned just lifting the power pin
<Habbie>
so you can power the spi without powering the board
<Habbie>
(I have not tried it)
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<aparcar>
what is the version schema of dsl_vr9_firmware_xdsl?
<aep>
jo anyone knows how the watchdog on mediatek ralink works? it's broken for me on WE1026 and the DTS doesnt match the vendors pin table
<aep>
but apparantly it worked for whoever submitted the patch
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<neggles>
aiyion: there is often a 0-ohm resistor connecting the power pin of the flash chip to the rest of the circuitry, especially on boards with multiple footprints for one chip
<neggles>
if there is, you can remove that, read chip, then reinstall
<aiyion>
neggles thanks, will look out for it.
<neggles>
it's usually not worth the effort, SOIC-8 and SOIC-16 chips aren't particularly difficult to remove if you have some decent solder wick and/or a hot air gun
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<neggles>
I used to try to avoid it, but it's almost always quicker to just add some leaded solder to the pins, wick it off, and remove the thing than go hunting for other methods
<neggles>
aiyion: you can also try pulling the CS pin high with a 1K resistor, power up the board, wait a few seconds for the SoC to fail to read the boot flash (and hopefully hang), then power up the programmer
<neggles>
most semi-recent SoCs will self-reset rather than hang though
<neggles>
and yeah, like Habbie said, you can wick/lift the power pin, put a little piece of tape under it so it can't contact the pad, then attach the SOIC clip
<aparcar>
anyone got an old APU board to sell? I want to setup a labgrid
<aparcar>
stintel: I'm guessing dangowrt would know more about it?
<stintel>
aparcar: already found it (answered my own question with the commit hash)
<aparcar>
stintel: ;) gotta love git
<stintel>
well it helped that I remembered Daniel fixed it
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<zorun>
aparcar: you want one? I can give you an APU1 if you want
<zorun>
or do you need an APU2?
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<neggles>
hurricos: they have insisted to me in emails that they are still working on it / have contracted an external dev
<neggles>
and for octeon 3 i believe it since those are inside a *lot* of fairly expensive devices with end-of-support dates over 5 years away
<neggles>
and theyre still technically a current product
<neggles>
but... well we'll see I guess
<neggles>
aiyion: my fix for the 'desoldering other things nearby' problem is to apply some leaded solder to the leads of the flash chip, wick all the solder off, then reapply a tiny bit of leaded solder, add some flux, and use a low airflow setting; the leaded solder will melt long before the lead-free on the surrounding components, and low airflow prevents
<neggles>
them blowing away even if it does melt
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<enick_479>
zorun: hey this is aparcar with a broken matrix account. Either is fine, the performance for lan and wifi testing should be roughly the same right? I’d by some wifi 6 card for it
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<rsalvaterra>
enick_479: A glitch in the Matrix? ;)
<enick_479>
rsalvaterra: the bridges seem to be a matrix of glitches itself :(