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<iocampomx> dwfreed: It's running, here the config I'm currently using: https://pastebin.com/nHagHBx4. Any advice?
<dwfreed> did you actually restart the sqm initscript after changing the config?
<hauke> I prefer to just activate the lantiq/xrx200 subtaregt again, even when we still see error messages, see https://github.com/openwrt/openwrt/pull/13638
<iocampomx> dwfreed: Yes, I did `/etc/init.d/sqm restart`, SQM: Starting SQM script: piece_of_cake.qos on eth0, in: 50000 Kbps, out: 10000 Kbps. SQM: piece_of_cake.qos was started on eth0 successfully
<iocampomx> Also, on this router, lan is running on `eth0.1` and wan on `eth0.2`, but in the SQM config file I've `eth0`, if I put `eth0.2` it doesn't work
<dwfreed> well, vlans definitely work generally for sqm, as I use them
<dwfreed> hauke: could you put the dmesg output in a code block (surround with ``` at top and bottom)? GitHub is converting :de: into the german flag
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<rmilecki> iocampomx: one more thing, you still didn't share your dts with "fixed-layout"
<rmilecki> can you do that?
<iocampomx> Sure, let me finish few experiments. Quick random question, Do you know how can I check if the chipset support hardware offlodaing?
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<rmilecki> iocampomx: data sheets? ;)
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<SpectreDev_01> Can we unlock 160mhz band ona router that supports it but isn't enabled in stock
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<mrkiko> SpectreDev_01: depends on how th restriction is enforced
<SpectreDev_01> Hmm
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<Ansuel> rmilecki ping?
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<rmilecki> Ansuel: pong
<Ansuel> hi some times ago I sent some patch for the ubootenv nvmem driver
<Ansuel> did you found time to check them?
<rmilecki> Ansuel: sorry, i didn't
<rmilecki> i thought Rob had some objections
<rmilecki> did he?
<Ansuel> he never answered to the explaination tho
<rmilecki> that u-boot,env-size makes sense I think
<rmilecki> we need to convince Rob
<rmilecki> I'll see if I can support it with some arguments later
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<rmilecki> hopefully today
<Ansuel> thanks think he is a bit confused but the idea of having mtd of one size and ubootenv actually of another
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<kopijahe> Hi, I'm trying to port an ipq4028-based router to openwrt, I managed to boot openwrt 21.02 initramfs for "Qualcomm Atheros AP-DK01.1 C1" on it. Here's the stock and openwrt boot log, and extracted dts from stock kernel: https://gist.github.com/kopijahe/1bed6d1d261a9e131f862aca2869af76 And here's some photos: https://imgur.com/a/YayazVJ
<PaulFertser> kopijahe: hey. Do you need a wiki account to start documenting that? If yes, send me your desired nick and e-mail.
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<kopijahe> How can I translated the stock dts to comply with openwrt? I'm confused on the gpios thing
<PaulFertser> kopijahe: what exactly is confusing for you there?
<kopijahe> PaulFertser: I already applied when porting Bolt Arion (mt7621-based)
<kopijahe> PaulFertser: In the stock dts, it says like this: cs-gpios = <0x0d 0x0c 0x00 0x0d 0x2d 0x00>;
<kopijahe> but in dts that I read from openwrt, it says something like this: cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
<kopijahe> how can I translate that?
<kopijahe> I'm currently studying the dts from "qcom-ipq4028-wpj428.dts", "qcom-ipq4019-unielec-u4019-32m.dts", "qcom-ipq4018-gl-a1300.dts", and "qcom-ipq4018-eap1300.dts"
<PaulFertser> kopijahe: in stock dts you see decompiled data, so it depends on exact layout the obects got translated to.
<PaulFertser> The first bytes are a pointer to the object defined elsewhere in the DT.
<ukleinek> kopijahe: if you want a future prove approach, don't use gpio pin numbers at all.
<kopijahe> ukleinek: what is the future-proof way for doing this?
<ukleinek> kopijahe: otherwise don't try to understand the dtb, better look in /sys/class/gpio
<PaulFertser> kopijahe: but you already know gpio number, isn't 0x2d it?
<ukleinek> kopijahe: use /dev/gpioctrlX
<kopijahe> PaulFertser: ok
<PaulFertser> kopijahe: feel free to pastebin full decompiled DT for the reference and share here
<ukleinek> PaulFertser: if you get that guess from: cs-gpios = <0x0d 0x0c 0x00 0x0d 0x2d 0x00>; then you're wrong, that's the offset in the gpio-controller, not the absolute pin number
<PaulFertser> ukleinek: but kopijahe doesn't need an absolute pin number for anything
<PaulFertser> Only offsets from the pin controller matter.
<kopijahe> PaulFertser: Here it is: https://pastebin.com/80V3mZyG
<PaulFertser> (unless one wants to use old sysfs gpio export)
<ukleinek> PaulFertser: then you're right
<ukleinek> that makes me remember that I should refresh that dtc patch that makes decompiling resolve phandles.
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<hurricos> Mangix: I have apm821xx ar8237 (non-n) devices in active use (MX60)
<hurricos> I don't want to kick the can down the road, I have 3 on my desk and time in the upcoming month to yank and test
<hurricos> I just don't have the energy to bang my head against compilation attempts. A shitty (but compiling) device tree to start with would be appreciated
<hurricos> qca8k/dsa device tree*
<Mangix> sure I can do that
<Mangix> I can compile firmware if you want
<hurricos> compile and give me `git format-patch -p1` :^)
<hurricos> I just know I will be challenged trying to adjust the device tree and build options for qca8k
<Mangix> sure. it'll be in my github tree anyway.
<hurricos> but I can absolute a/b test and, even, provide you SSH access to a tftp server with serial and power switch access to one, if you're interested.
<hurricos> doubt that will be needed as I can test pretty quickly.
<hurricos> I believe almost all qca8k ports require manual intervention to rework switch configuration, yes?
<hurricos> s/qca8k/dsa/
<hurricos> eh, cross that bridge when we get there
<hurricos> just needs a compat version bump in the build.
<Mangix> I have the script that translates it
<hurricos> That's news to me, and I appreciate it.
<Mangix> Unknown val: 0x7f7f7f for reg: 0x624 <-- I forgot what this was
<Mangix> ping @Ansuel
<Mangix> erm Ansuel
<Ansuel> pong?
<Ansuel> let me check
<Ansuel> isn't that LED?
<Ansuel> GLOBAL_FW_CTRL1
<Ansuel> you can ignore
<Mangix> OK
<Mangix> hmmm this dts is interesting
<Mangix> no mdio0
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<Mangix> this switch config is broken. has 1 CPU port but specifies 2
<Mangix> Ansuel: if there's no mdio0, where does the switch section go?
<Ansuel> link to the dts?
<hurricos> Mangix: if I'm not mistaken the SoC has two gigabit switch ports on it
<Ansuel> why do you say specifies 2 ?
<Ansuel> also the pad regs might also be set just for the sake of it and lazyness by the dev
<Ansuel> the important part is the type and the delay
<Mangix> script says Conf for cpu port0, Mode rgmii-id, With tx-internal-delay-ps of 2000
<Mangix> Conf for cpu port6, Mode rgmii-rxid
<Ansuel> and sgmii configuration
<Mangix> hurricos: I don't see a second one anywhere
<hurricos> I have poor memory - there is only one. I think I recalled u-boot doing a lot of handling of the switch.
<hurricos> RE: is only one: block diagram: https://www.rlocman.ru/i/Image/2010/04/20/APM82181.JPG
<Mangix> all 5 ports are handled by qca8327 from what I see
<Ansuel> if there is a second cpu port to test it's doable, but that rgmii-rxid thing is test for port5 stability
<Ansuel> it's already handled in the code internally
<hurricos> ACK. I misremembered some switch-and-cpu implementations using two sets of *gmii between switch and soc
<Mangix> I only know of some ath79 and ramips devices with dual switches
<Mangix> Ansuel: anyway, got an idea on the mdio thing?
<Ansuel> what do you mean?
<Ansuel> by the looks of it is a mac with integrated mdio and on that is connected the qca8k switch
<Mangix> on ath79 and from what i see ipq806x the switch node is under mdio0 and referenced by the MAC
<Ansuel> so i guess it would use the same structure with the swconfig part replaced with the qca8k part... and cpu0 with the ethernet binding pointing to emac0
<Ansuel> and emac0 phy-handle binding dropped
<Mangix> so put switch under mdio?
<Ansuel> yes
<Mangix> the phy ports as well i'm assuming
<Mangix> wait a minute...
<Mangix> I see ucidef_set_led_switch but dts says they're GPIO...
<Mangix> hurricos: what color are the leds?
<hurricos> Mangix: Green, with the exception of power which has an alternate amber behind it as well
<hurricos> RE: color.
<Mangix> yeah. they're GPIO not switch controlled
<Mangix> 01_leds is wrong
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<Mangix> what is this DEVICE_COMPAT_VERSION ?
<Ansuel> should be documented on the wiki
<Ansuel> it's a way to prevent upgrade or warn the user that the image he wants to upgrade is not compatible and some action are required
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<Mangix> patch is done. Now time to compile toolchain and be sad when it fails to compile
<Mangix> oh this is powerpc
<Mangix> so it'll fail like with ath79 probably
<Mangix> then again the turris people tested it there
<Ansuel> Mangix if you don't want to compile toolchain
<Ansuel> try the external one
<Ansuel> :D
<Mangix> it's almost done
<Mangix> I smell smoke and hear firetrucks a few blocks away. Oh boy....
<Mangix> hmmm what's a good way to host files?
<Ansuel> Mangix big flame?
<Mangix> probably small.
<Mangix> although for the smell to reach here...
<Mangix> so this is interesting
<Mangix> this target basically has two switches
<Mangix> I wonder if it's possible to convert the realtek one. AFAIK, the upstream driver supports it.
<Ansuel> realtek...
<Mangix> uhh
<Mangix> switch is 8367. upstream supports 8365 and 8366.
<Mangix> oh it supports RTL8367S but RTL8367RB is used here
<Ansuel> rb = real bad?
<Ansuel> :D
<Mangix> above my pay grade
<Mangix> Ansuel: what was package48 again?
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<Ansuel> some switch have different chip format/pin count
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<Mangix> can't find that dts binding. i think it was renamed
<linusw> I'm removing GPIO numbers all the time, OpenWrt has libgpiod and the gpiod-utils available for the occasional userspace hack.
<Mangix> oh defaults to on
<Mangix> hauke: https://github.com/openwrt/openwrt/blob/main/target/linux/lantiq/xway/config-5.15#L2 seems to be a mistake. I don't see any lantiq device using this.
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<hauke> Mangix: I think some atheros PHYs are used by some Lantiq devices, but I do not know if the xway boards are using this PHY
<Mangix> if atheros PHYs are used with atheros switches, I don't think lantiq has any
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<hauke> Mangix: there are some xrx200 devices using the lantiq gswip with atheros 1G PHYs
<hauke> AVM did this on multiple devices
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