ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<kgarrington> kode54: sentences like “I disable selinux on centos server” are often followed by “we were hit by an incredibly sophisticated cyber attack” :p
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<psykose> guess they got hit by a really sophisticated cyber attack..
<kode54> Yeah, right
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<mps> kode54: heh, I'm maintainer for linux-edge (latest stable mainline) for alpine linux which have moto: small, simple and secure, and also don't enable SELINUX
<mps> most of these things are so called 'security theater'
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<jannau> marcan: failed display init on the ultra was my fault, DVA was wrong for the ultra as it has 1 additional page mapped compared to the mac mini
<jannau> I've pushed updated m1n1 t6002-bringup, additional changes: skip initialization of interrupts on die 1 and cosmetic fixes
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<robinp> any hints on building custom kernels. I keep getting snagged as its trying to load the initramfs. Are there any tricks here ?
<robinp> mps: ok I was using that config, but is there more I need to notice.
<mps> robinp: depends on your build machine and distro
<robinp> mps: MBP M1 Pro, just using the default Asahi Desktop
<mps> robinp: so arch distro, I think you don't need anything special, if you installed arch build environment ofc
<psykose> mkinitcpio should do it for you when you install the kernel you built
<psykose> (as a package)
<psykose> if you are just copying the kernel files around manually, then you need to manually invoke mkinitcpio with whatever it needs
<psykose> but if you use makepkg -si or whatever that should just be done for you
<robinp> psykose: ah ok - I was makepkg -s then manually installing with packman -U *xz
<psykose> that should also still work
<psykose> afaik mkinitcpio should still print something on the screen that it does stuff
<psykose> the only other thing i can think of is everything is actually handled fine, and it is merely broken because your config can't actually boot after the initrd load
<j`ey> yeah, I think we need more details about where its breaking, what changes you made to the config etc
<chadmed> keep in mind that it could be crashing for a billion reasons, it crashes on grub saying loading initramfs because it crashes before linux even has the framebuffer
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<chadmed> so you might have borked something important
<robinp_> the config is just from https://github.com/AsahiLinux/PKGBUILDs/blob/main/linux-asahi/config and the only change I made was the i2c patch
<j`ey> I would first try to build that package without any modifications
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<sven> i need to find a better mail client and a way to separate these LKML mails from my other emails *sigh*
<mps> mutt? ;)
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<jannau> if you want to have mails completly separate you could use lei to retrieve them from the mailing list archives: https://people.kernel.org/monsieuricon/lore-lei-part-1-getting-started
<sven> don't think that works all that well for review comments to my patches which will be sent to me directly ;)
<jannau> it will not work for review comments sent to you alone. for everything else you could filter for messages with your email address in to: or cc:
<YichaoYu[m]> is anyone familiar with ldnp instruction?
<YichaoYu[m]> but is it suggesting that the re-ordering is visible for a single thread?
<sven> alright, fingers crossed I didn't forget to reply to any of the nvme comments
<jannau> there's a new comment, shmem_setup() has the iova argument for dcp
<sven> :D
<sven> I was thinking to already pre-fill bfr->iova and then shmem_setup() is just "do whatever is required to make bfr useable"
<kettenis> YichaoYu: The ARM ARM is a bit more explicit about this
<kettenis> but yes, it seems like LDNP doesn't "interlock"
<kettenis> which is ok I suppose since it isn't an actual load; just a hint
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<YichaoYu[m]> what do you mean by it isn't an actual load? I thought it will load and write to the registers?
<kettenis> hmm, maybe I'm reading this wrong
<YichaoYu[m]> I assume by ARM ARM you mean C3.2.4?
<kettenis> indeed
<YichaoYu[m]> I'm currently interpreting that as it doesn't satisfy the c++ memory_order_consume but I'm reading it again...
<YichaoYu[m]> yeah, since it says "by the other observers within ...."
<kettenis> and C6.2.129 makes it obvious it does indeed do the load
<YichaoYu[m]> (I wonder if there's a version difference... for B.b revision that's LDTRSW section)
<kettenis> hmm, wait
<YichaoYu[m]> (ok for me it was C6.2.98 LDNP) and I do interpret `X[t] = data1; X[t2] = data2;` as writing the load result to the registers.
<kettenis> looking at G.b here
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<YichaoYu[m]> (doubled page number.... ok)
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<kettenis> anyway, C3.2.4 talks about *other* observers withing the sharability domain
<kettenis> but the page you quoted does indeed seem to suggest that it actually affects the observer executing the code
<YichaoYu[m]> I don't think the page I linked make sense = = ......
<kettenis> ah, I think I understand now
<kettenis> so if there is a 2nd thread that writes to [X3] you may end up in the situation where LDNP loads from the old address at [X3] but X0 will hold the new address
<YichaoYu[m]> that'll still be very strange
<YichaoYu[m]> cuz how does ldnp decide what the old value of [X3] is, especially, say, when you also have a `add X0, X0, #8` between the two
<YichaoYu[m]> in this case, I feel like in order to get the wrong address it'd have to also either run the add with a wrong input or ignore it, which is even more insane
<YichaoYu[m]> my interpretation was that on a single thread the address it access should be consistent, but the thread may decide to access [X0], with the correctly loaded address, before X0 is loaded from [X3].
<YichaoYu[m]> (essentially that if the cpu predicted what X0 is correctly it could use a value it has cached for that from a minute ago, which it otherwise can't)
<kettenis> true
<kettenis> well, I mean, true that my interpretation is probably wrong
<kettenis> note that C3.2.4 talks about address dependencies
<YichaoYu[m]> yeah, which I interprete as memory_order_consume https://en.cppreference.com/w/cpp/atomic/memory_order and that seems to be what E2.3.2 is talking about
<kettenis> so actually what I think this means is that if [X3] and [X0] are overlapping memory addresses the values in X2, X1 and X0 are not necessarily consistent after the two instructions have executed
<kettenis> i.e. you may end up with old memory contents in X2, X1 and new memory contents in X0
<kettenis> I don't understand the C++ memory ordering semantics ;)
<YichaoYu[m]> that I agree, but X2 and X1 should still be loaded from what X0 ends up being
<kettenis> right
<YichaoYu[m]> (and I assume for a single thread with no race it should still be deterministic......)
<sven> jannau: my memory is a bit fuzzy, but were you also able to reproduce that weird missed nvme interrupts bugs when there was no spinlock around command submission?
<jannau> sven: yes, with m1 max. I heven't really tried to reproduce it on the mac mini
<sven> can you reproduce it reliably there?
<j`ey> shmem_setup() is omnipotent :D
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<jannau> sven: with the patch not reproducible so far, I'll test how fast I can reproduce it without those writel
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<jannau> sven: or not although the error looks different: "nvme nvme0: Device not ready; aborting reset, CSTC=0x3"
<sven> ah, too bad.
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<rqou_> does anybody know how i can actually get the m1 max prores hardware to be used? attempting to use ffmpeg -vcodec prores_videotoolbox just gives a very unhelpful "Error while opening encoder for output stream #0:0"
<ChaosPrincess> maybe try imovie?
<rqou_> uhh, how do i export something from imovie?
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<rqou_> ok, apparently -pix_fmt yuv420p solves it (-pix_fmt bgra doesn't work for reasons i don't understand)
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