<_jannau_>
I guess by testing to write an read back for an increasing number of SIDs. the thunderbolt darts have 64 SIDs
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<maz>
_jannau_: that's what the PCIe driver does.
<millenialhacker>
I think ISP also have more than 16
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<jannau>
maz: doesn't the PCIe driver looks it up in iommu-map
<jannau>
millenialhacker: judging by "dart-tunables-instance-X" in the adt there are 3 dart instances for isp. compare with 2 instances for the usb-c ports
<sven>
PCIe figures out 16 vs 64 (or whatever number) inside the rid2sid map by testing which regs are writable
<sven>
with DART I did the same but within Python and 16 is hard coded for now
<sven>
Im willing to be the sid count is also encoded in one of the DART_PARAM regs at the start though
<sven>
and iommu-maps is then consulted to figure out which pci device number is supposed to be mapped to which sid
<kevans91>
ah, interesting
<kevans91>
er
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<millenialhacker>
yeah i noticed that sometimes these three darts are are using same translation tables
<millenialhacker>
sometimes not
<millenialhacker>
but i see sometimes dart regs are written with same values like when we set TTBR[0-16] in other offsets which makes me thing there more supported SIDs on those.
<millenialhacker>
BTW I just repurpose DART mapper in my branch to monitor six darts instances at same time, so I know those extra offsets do not belong to other DART from ISP.
<millenialhacker>
same with TCR, i see the values when TCR is set written in other offsets as well
<millenialhacker>
should corellium codebase be treated specially like copyright disclaimer suggests? sven, marcan?
<sven>
for usb XNU just mirrors the writes and pagetables for both DART instances, might just be the same for ISP
<sven>
i haven't seen anything problematic from a copyright standpoint inside corellium's code but I generally avoid looking at it because it's just a PoC and can give you the wrong idea about how to write a sane driver
<sven>
i think marcan's policy is to treat it as if you were reading decompiled XNU assembly though
<millenialhacker>
sven that makes sense, I noticed that independently of the DART instance, if I do IOREAD on them using a IOVA I always get same data, which made me thing they were using same page tables.
<millenialhacker>
sven, regarding corellium, I just noticed they initialized iommu driver instance with some data regarding number of SIP supported by DART instance, so I wonder if we can at least see how they did it.
<sven>
see, that's why I recommend to not look at that code because it can confuse you
<sven>
they just pass 16 or 64 as a custom DT property IIRC which is not how you do it
<sven>
either it's possible to get the number of SIDs from one of the early DART registers, or we check how many TCRs we can access, or we just add another compatible for the 64bit DART i
<sven>
erm, s/64bit/64 SID/
<millenialhacker>
ty, now I got your p\];p['
<millenialhacker>
point*
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<jannau>
sven: boots and mount root fs from nvme, (asahi branch with bits/050-nvme replaced by nvme-v3, smc-rtkit disabled, no dcp)
<sven>
awesome, thanks!
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<sven>
rtkit had no functional changes from v2 fwiw, just added _ULL to the GEMASK defines
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<nicolas17>
macOS 15.5 beta 3 is out
<jannau>
12.4 I pressume
<nicolas17>
yes ugh
<nicolas17>
I'm confusing things because the studio display firmware also has a beta out and it matches iOS versions
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<jannau>
sven: was your aes experiment working without dart bypass?
<sven>
you need to write to that stream enable register as well
<sven>
Pretty sure that’s still missing from that old code
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<jannau>
I switched to dart.py to test it on t6k so that should take care of that and it enables stream_id 1
<sven>
I never tried that old script with translation because I didn’t know about that stream_enable register so there could be also some other issue
<jannau>
works now after a reboot, seems broke it
<sven>
it essentially has a command fifo, wouldn’t surprise be if you need to reset it if a command in there gets stuck
<jannau>
works on t6000 as well
<jannau>
read and write protect bit on dart-t6000 verified
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