ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<jannau> marcan: how much effort is it to recreate KNOWN_MSGS in trace_dcp.py? I think '"A103": "IOMFB::UPPipe2::test_control(IOMFB_TC_Cmd, unsigned int)"' doesn't exists anymore
<jannau> signature still matches but looks more like it should be 'A103 = Call(void, "get_config_frame_size", width=InOutPtr(uint), height=InOutPtr(uint))'
<jannau> CALL > 0x0000002000400002 CMD 0x40 A103 0xc 0x8 00000000000000000000aaaa
<jannau> the next two calls set_config_frame_size and program_config_frame_size are consistent with one removed call
<jannau> not a particularly important task but it's impossible to tell from traces what happened to unobserved calls/callbacks
<jannau> the next observed Call A131 doesn't look obviously wrong judging by context
<jannau> at least dpms and switching between 2 different seems now to work reliable
<j`ey> between 2 different whats?
<jannau> displays
<j`ey> with different resolutions?
<jannau> yes, a cursed dell 4k display and a well behaved FullHD display
<sven> sounds like we have the same dell display :D
<jannau> kde system settings seems to get confused about the refresh rates though. 4k is limited to 30 Hz due to HDMI 1.4 but it offers 60, 50 and 24 Hz instead of 30, 25 and 24
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<j`ey> sven: r-b by hch.. nvme seems pretty close now!
<sven> yeah, just dt-bindings and SART/rtkit now :)
<sven> in other news, acio ofc has another tunable format compared to atcphy *sigh*
<j`ey> talking of tunables, I get this warning when building m1n1 now, not sure which type should be changed:
<j`ey> src/kboot.c:710:51: warning: comparison of integer expressions of different signedness: ‘int’ and ‘size_t’ {aka ‘const long unsigned int’} [-Wsign-compare]
<j`ey> 710 | if (tunable->offset + (tunable->size / 8) > tunable_info->reg_size) {
<Dcow[m]1> sven: acio?
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<marcan> sven: can we convert the tunables to some common format in m1n1?
<sven> marcan: yes, that already happens for the atcphy ones
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<sven> im just annoyed I have to write another converter and can’t just reuse the one that already exists
<sven> Dcow: thunderbolt
<sven> j`ey: huh, let me fix that
<sven> j`ey: uhh.. i'm a bit confused. tunable->{offset,size} should be u32 and tunable_info->reg_size is size_t and unsigned as well.
<j`ey> sven: yeah but '8' is an int!
<j`ey> 8u fixes the warning, heh
<sven> huh. which compiler is that?
<j`ey> aarch64-linux-gnu-gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0
<marcan> 11.2.1 throws no warnings for me
<sven> apple's clang 12.0.5 also doesn't
<jannau> the 8 should be promoted to unsigned as 'int' and 'u32' should have the same rank
<j`ey> let's just assume it's funky in the build of gcc I have then
<marcan> I can't repro on godbolt on 9.4 either
<j`ey> nor me, I was just trying that
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<marcan> though that seems c++-specific
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<marcan> jannau: pushed your t6k2 stuff to main, with some adjustments
<marcan> let me take a look at that DCP thing
<marcan> jannau: https://mrcn.st/p/36QzY3JG partial dump
<marcan> let me know if you need more; it's not 100% automated
<jannau> marcan: thanks, t6k2 looks good. note that macos guest panics due to the initialized display
<marcan> yeah, need to look into that
<jannau> AMCC0 PLANE0 UNEXP_RT_HIT_DIR error: INTSTS1 0x00000100 AFERRLOG0/1/2/3/4 0xfff47500/0xea10f/0x23a120e/0x80/0x80041 ADDR 0x10ffff47500 CMD/SIZE 0x14(ncrdincr_ro)/0x7 AID/TID 0x120e/0x23a @AppleT6000PlatformErrorHandler.cpp:2712
<marcan> did we set the uncached mode thing in the DART FB mapping?
<jannau> 0x10ffff47500 is within the first dart-disp0 page table
<marcan> dart->l1[ttbr][idx] = offset | DART_PTE_VALID;
<marcan> I suspect that's wrong since DART_PTE_VALID sets both bits
<marcan> we might be mapping the *page tables* themselves as RT
<marcan> or maybe they are supposed to be RT, and having them in CPU cache also is a no-no?
<jannau> the page table itself is initialized by iboot
<marcan> but we write it, right?
<marcan> so we probably need to map it uncached
<millenialhacker> Hi! here working on ISP, I notice a memory address which gets written always with a incrementing value but step between value and value is not constant. Have you ever seen a similar pattern?
<millenialhacker> e.g: https://pastebin.com/vAJ8AmHz
<sven> could be a ringer buffer that gets advanced, or maybe some timeout. hard to tell without context
<jannau> I tried that and it didn't made a difference
<sven> that address is *read* and increases. looks like a counter at first glance
<jannau> also bit 1 (uncached for t6000/t8110) is not set: table (0): 00000000 ... 02000000 -> 0000010ffff44000 [01]
<millenialhacker> sven: ring stuff makes sense, it always come back to lower addresses after some time
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<jannau> marcan: dcp method annotations are good, I haven't spotted any other inconsistencies. thanks
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<millenialhacker> sven: definely some kind of counter, timer, each 3 mins it does a full cycle and next subsequent word (+4 bytes) get incremented in one.
<sven> sounds like some timer based on that 24 MHz clock then
<millenialhacker> sven: how did you get is related to 24Mhz clock?
<millenialhacker> Sorry for the question, just curious, trying to learn here
<jannau> should loop every 178.957 seconds
<sven> because 2**32 ticks with a 24 MHz frequency take about 3 minutes ;)
<j`ey> and there is a 24Mhz clock that's used by several things already!
<sven> and I just happened to know that by heart because I wrote the watchdog driver where I did that calculation
<millenialhacker> holy cow guys, I didn't spot that one
<millenialhacker> I was planning to count number of reads per second
<millenialhacker> but I'm almost sure all of you are right, so no need to do the math
<millenialhacker> D:
<sven> you already know that a full cycle takes 3 minutes. a full cycle is 2**32 events, i.e. 2**32 / 3 minutes which is ~24 MHz
<sven> (note that it's actually not a full cycle but a 64bit counter but same difference)
<millenialhacker> sven: yeah, it seems next 4 bytes are just the upper bits of the 64 bit counter
<millenialhacker> should I document that stuff, right?
<j`ey> yep
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<marcan> jannau: fixed the macos thing. It's what I said; we need to map the pagetables as UC, since DART page table walks count as part of the realtime path, same as the framebuffer itself, and cannot hit the CPU cache.
<marcan> there's a flag in pmap-ranges that I'm guessing tells us that; alternatively we could use the real-time DART property and the l2 ranges thing
<marcan> this won't work (right now) if we have to allocate our own page tables, of course
<jannau> marcan: thanks. format check failed
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<marcan> right..
<j`ey> ooh tick polling
<marcan> or rather, not
<marcan> jannau: hopefully HV should scale to t6002 core counts better now
<marcan> it no longer tries to take a single lock 20000 times per second :p
<marcan> (only 1000 and from the same CPU in the easy case)
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<sven> someone should pick up that t6k dart series and correctly add support for that new PTE format now that we know these bits
<marcan> yeah
<marcan> though the uncached bit seems unrelated here?
<sven> iirc there’s a flag that can be passed to map something as uncashed
<marcan> the issue I fixed was just the MMU mappings
<sven> oh, just in general
<marcan> not sure exactly how that uncached bit interacts
<marcan> but yeah
<sven> read/write protection also changed iirc
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<jannau> marcan: yes, macos HV is much faster. linux seems to be faster as well although it was less noticeable
<jannau> only annoying case was window resizing/moving which could have been caused by dcp tracing
<marcan> everything should be faster in general, I think macos is just heavier so becomes even worse when everything is fighting
<marcan> jannau: whoops, forgot a thing, pushed a fix
<marcan> hopefully I didn't slow it down again :)
<marcan> (it wasn't properly running the tick on secondaries)
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<marcan> heh, missed a thing, force-pushed the fix to properly fix it now
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<jannau> shutdown/restart is slower but still reasonable fast
<millenialhacker> regarding isp, I noticed a pattern of access some memory regions that get's repeated over and over. :D
<millenialhacker> I actually copy pasted the logs, and then selected like 50 lines of memory accesses and then find them using VSCode and they get repeated over and over.
<millenialhacker> so I'm wondering if this could be some kind of polling between host and ISP
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<millenialhacker> e.g. https://pastebin.com/2QWrf2vi
<millenialhacker> holycow, I think the pattern repeats over each camera frame
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<sven> urgh... usb4/thunderbolt is going to be nvme all over again. the current driver only supports PCI.
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<kettenis> sven: took me a few seconds to realize what you were trying to say there
<sven> ah. yeah, that sentence is more than a bit confusing.
<maz> sven: hopefully there will be less opposition this time around. I remember looking at the Corellium hack, and it didn't seem to have a massively different programming interface.
<jannau> is there even usb4/thunderbolt HW beside Intel (and apple)? zen4 will be pcie based too
<jannau> maz: Corellium had/has usb4/thunderbolt support?
<jannau> indeed, the last thing they added
<sven> didn’t look at the corellium thing yet. I first want to figure out which crimes I’d commit against drivers/thunderbolt before I look at that ;)
<sven> but apple’s NHI doesn’t look too different from what I can tell
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