ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<nicolas17> https://twitter.com/tech_reve/status/1702097480924741873 there's some evidence that A17 has the same CPU cores as A16
* kevans91 ponders using stackable headers for the middle board in a stacked setup
<nicolas17> marcan: just for your curiosity ^
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<elros> Hey there, I'm unsure if this is the right place to ask, but given what's written in the contributing page, I wanted to get familiar with asahi in order to contribute by looking at the docs and helping out there. But I'm unsure on what repo exactly should I contribute. Or would it be more efficient to just look at issues on the repos under the org?
<elros> In any case, would like to help any way I can. I am a beginner at this, however. My experience is as a web dev, mainly. I do some C programming as part of my studying efforts, on the side, but that's about as familiar as I am with things at lower levels than web...
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<chadmed> elros: i think the best place to start would be the yaks page, https://github.com/AsahiLinux/docs/wiki/Yaks-in-need-of-shaving
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<chadmed> whats going to be the best way to do the dt schema for the smc hwmon stuff? rummaging around it looks like its probably best to write one for the whole SMC and put it under mfd
<chadmed> but im open to suggestions
<nicolas17> ok I'm seeing conflicting info about A17 now so nevermind
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<elros> chadmed: Thanks a lot! But I did look at that page. The thing is I don't think I have enough knowledge to claim any of the unclaimed issues. Which is why I was kind of trying to go for docs.
<elros> Looking at those issues I'm unsure where to start
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<chadmed> tested on j415 and j314, been meaning to get the mac mini going too but couldnt really drag that with me to hospital :)
<chadmed> im sure there are probably issues with it though so further testing would be nice :)
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<elros> I see... maybe I can help with that. I only have an M1 available, though. I might be able to test on an M2, but I was unable to install the fedora remix on it.
<chadmed> it should work regardless of soc, what we need to figure out is which smc keys we are going to expose for which devices
<chadmed> because theres like 99999 grillion keys
<chadmed> but not all of them expose user-helpfuk information
<chadmed> helpful*
<chadmed> only thing im really not too sure about is all that horrid pointer voodoo in macsmc_hwmon_populate_info
<chadmed> there just *has* to be a better way to do that
<elros> Ok. Which brings me to my next question: where can I read up to understand what are these keys and even to be able to understand this file, for example: https://github.com/chadmed/linux/commit/fa332c54cae797dc03a1db6601057d098ab01d88
<j`ey> chadmed: nice work
<chadmed> j`ey: thanks :)
<chadmed> first real attempt at kernel work that isnt rearranging a for loop so it probably needs work
<elros> chadmed: thanks!
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<elros> chadmed: How do you test these things? I found this page: https://github.com/AsahiLinux/docs/wiki/Low-level-serial-debug
<elros> But I'm thinking that's probably not how to do it?
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<elros> I guess the specific question is how do I do to read whatever info the hardware is printing out. In the HW:SMC page there are mentions of reading and writing, but I couldn't find out how to read and write. Nor if this is doable on a terminal emulator, for example
<_jannau__> for testing kernels most of us probably use something along https://github.com/AsahiLinux/docs/wiki/Tethered-Boot-Setup-(For-Developers)
<_jannau__> probably with m1n1 installed in proxy only mode in a separate partition or m1n1 installed in a macOS partition for running macOS under the HV for tracing
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<j`ey> elros: you can't do it via linux terminal (as is, I had at some point some patches to add a debugfs to the SMC stuff so you could access all the keys..)
<j`ey> easiest way is to use m1n1 to read them (and they are some examples in the experiments/ folder in m1n1)
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<elros> Aaaah, nice to know. And sorry if my questions are basic. I really have 0 knowledge on how to work with these things. Thanks a lot everyone!
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<ydalton> i have a question, where do you find the compiled dtb files? i can't seem to find them in the /boot folder. are they embedded in the kernel? uboot?
<mps> ydalton: depends on distro kernel, i.e. how it set where to put dtb files
<_jannau__> they are embedded in ESP/m1n1/boot.bin, location in the system is distro specific, check the update-m1n1 source and/or config
<mps> usually /boot/dtbs-...
<_jannau__> I think asahi alarm installs them in the module dir
<mps> ah, interesting
<ydalton> there's no /boot/dtbs-... folder in my installation
<ydalton> boot.bin is just m1n1 right?
<ydalton> second stage m1n1
<mps> boot.bin is m1n1+u-boot=dtbs
<mps> s/=/+/
<ydalton> ah
<_jannau__> s/u-boot/next stage payload (usually u-boot)/
<ydalton> but it could be a linux kernel if you really want it to be
<ydalton> right?
<ydalton> ah, i see on the wiki
<_jannau__> yes, in that case you probably want to append boot args as well
<_jannau__> you can also append an initrd
<ydalton> ah i see it here
<ydalton> can you use the chainload script to chainload m1n1 with the bootargs, dtb, linux kernel and initramfs?
<ydalton> i figure it should work
<j`ey> yup
* _jannau__ should prepare the initramfs hooks to copy kernel modules into a tmpfs for the live system
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<ydalton> hi, i was reading up on aarch64 assembly, and it said the W registers are just the 32 bit half of the 64 bit of the X registers, similar to rax and eax in x86_64 assembly. i looked at an assembly file in m1n1 and noticed it used the W registers, but i thought apple silicon does not support 32 bit arm!
<j`ey> it supports 32bit registers still
<j`ey> rather: aarch64 architecture includes 32-bit registers
<j`ey> (and instructions that operatre on 32-bit quantities)
<j`ey> but the m1 doesnt support the aarch32 ISA
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<_jannau__> nicolas17: on one hand possible, ~10% faster but almost 10% max perf core frequency, 20% faster GPU after updating from 5 to 6 GPU cores. But I doubt apple would have talked about wider decode/execution units in the presentation if the cpu core were identical
<nicolas17> ydalton: a hypothetical x86_64 CPU that doesn't support x86 (32-bit) instructions would still have eax, ax, and al/ah
<nicolas17> _jannau__: guess we have to wait for the software to be out to figure out the core codenames
<nicolas17> (iOS 17.0 RC does not include the new iPhones)
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<ydalton> i think i understand
<ydalton> but like if you don't have instructions to use them, do they really exist?
<nicolas17> I think you misunderstand what "64bit instructions" means :P
<_jannau__> most aarch64 instructions can operate on x and w register (aliases)
<ydalton> nicolas17: if i understand what it means, it's instructions that operate on 64 bit wide registers?
<_jannau__> aarch32 has no w registers. it uses rX mnemonics since all registers are 32-bit wide
<ydalton> yeah, i've seen those r registers before
<ydalton> i was today years old when i realized the r registers are the w registers in aarch64
<ChaosPrincess> in case of x86, 64 bit instructions are just 32 bit ones, but with a REX prefix in front of them, in case of arm32/aarch64, the instruction sets are quite different, and
<ydalton> i think i get it now
<ChaosPrincess> i'd even say 32 and 64 bit arm are different instruction sets, with 64 bit just being vaguely inspired by the 32 bit one
<ydalton> it doesn't support arm executables
<ydalton> but you can still use the 32 bit wide registers
<ydalton> and arm64 32 bit code is completely different to regular arm code
<ydalton> is my understanding correct?
<ChaosPrincess> something like that, yes
<ydalton> and apple silicon doesn't support the latter
<ydalton> but you can still use the 32 bit registers
<j`ey> the 32-bit registers are part of aarch64 too
<sven> a bit of nitpicking: all aarch64 instructions are 32bits long, it's just that some of them operate on 32bit registers while others operate on 64bit registers
<ydalton> yeah, i heard and saw arm64 instructions are 4 bytes wide
<j`ey> it's not like theyre just 'leftover' or something
<ydalton> compared to x86 with their variable length instructions
<ydalton> y u no be simple arm/arm64
<ChaosPrincess> id say its x86 that is the weirdo
<sven> x86 is much much worse :D
<sven> yeah
<ydalton> well
<j`ey> ydalton: it is simple!
<ydalton> it had to hold cruft for nearly 45+ years
<sven> yeah, which makes it much worse than aarch64 which threw away the 32bit legacy imho
<nicolas17> fixed-length instructions are one thing letting ARM CPUs be faster
<nicolas17> I don't think it's a *significant* difference but it's one factor
<ydalton> well if you're not trying to decipher how long the next instruction is, when you can basically assume all instructions are 4 bytes wide, it's gonna be faster
<ChaosPrincess> that matters surprisingly little
<sven> it also helps that apple as an all time world-class hw team ;)
<sven> *has
<ChaosPrincess> a lot of hot code will run out of micro-op cache anyway
<ChaosPrincess> sven: throwing trucks full of cash at tsmc to get the best node doesnt hurt either :P
<sven> yup :D
<nicolas17> ydalton: you can decode more instructions in parallel if you don't need to figure out the length of one before you can start decoding the next
<nicolas17> but yeah I don't know to what extent instruction decoding speed affects overall speed
<ydalton> maybe aarch64 is just built better
<ydalton> but like if i look at x86 assembly to machine code (in hex), i can kind of guess how it all works
<ydalton> when i look at aarch64 assembly and its machine code it looks incomprehensible
<ydalton> also aarch32 has that weird thumb code thing
<sven> that just sounds like you're more used to x86
<sven> anyway, this is also pretty off topic at this point
<ydalton> whoops
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