ChanServ changed the topic of #asahi-gpu to: Asahi Linux: porting Linux to Apple Silicon macs | GPU / 3D graphics stack black-box RE and development (NO binary reversing) | Keep things on topic | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-gpu
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<marcan>
karolherbst: It's asymmetric signatures, there are no "signature keys" to leak. Apple are not Nvidia, they actually know how to design secure hardware.
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<marcan>
That is not to say there aren't any ways around that due to bugs... I found one... but it's not practical for firmware replacement.
<karolherbst>
:D
<karolherbst>
right...
<karolherbst>
but it also doesn't sound like it will be needed... hopefully. Tiled displays working is quite an optimistic sign
<marcan>
The problem is there is still one IOMFB, which means one "connector" in DRM parlance. Making it behave as two independent ones is... not going to be pretty.
<marcan>
I'm not even sure if it will work with non-identical monitors
<karolherbst>
yeah.. that's the important question here
<marcan>
Like, how does the top-level decide what "mode" to expose downstream? Does it rely on tiled display descriptors in the EDID? Do we need to start conjuring up weird EDIDs that merge the real EDIDs somehow and use the virtual EDID feature (I *think* that is a thing)?
<karolherbst>
I think the EDID is the same on both outputs
<marcan>
I suspect this is all going to be, if possible at all, a very, very limited hack (that probably shouldn't even be enabled by default)
<karolherbst>
there is just a property telling the OS that it's a tiled one
<marcan>
Right
<karolherbst>
though the firmware might just use one of those
<marcan>
but then that's the thing, you plug in two displays with two EDIDs, route them to separate pipes of the DCP, then what?
<marcan>
it probably just picks #0 and uses that
<marcan>
sees no tiled descriptor, refuses to use #1
<marcan>
fin
<karolherbst>
yeah...
<marcan>
so then what, we read the EDIDs manually via the EPIC i2c interfaces, and conjure up some "merged" EDID with a tiled descriptor, then inject that?
<marcan>
imagine the combinatronics...
<marcan>
I can see this being practical for the special case of two identical monitors with identical EDIDs
<karolherbst>
not sure messing with EDIDs is a sustainable plan...
<marcan>
yeah.
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<karolherbst>
impressive split
<karolherbst>
is there a way to configure the hardware behind the firmwares back?
<marcan>
yes, but it's easy to crash the firmware doing that
<marcan>
plus then that means we get to implement wonders like DP training
<marcan>
I'm not sure we want to go there
<karolherbst>
wondering if there is a way to put the firmware into a mode it ignores display related stuff
<marcan>
but yes, if we wanted to bypass the firmware, the only practical option is to just never power on the coprocessor and do everything ourselves directly against hardware
<marcan>
(which is possible)
<karolherbst>
and also not that much work actually
<marcan>
well... the megabytes of firmware beg to differ
<marcan>
there's a *lot* of stuff in there
<karolherbst>
yeah.. if it's either all or nothing I agree
<marcan>
and I certainly am not looking forward to reverse engineering clocking, training, RT bandwidth calculations, and all that nonsense
goldsoultheory has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
<karolherbst>
then it's probably better to use the firmware
<marcan>
(as insane as it is, yes)
<marcan>
plus, it abstracts out platform differences for us
<marcan>
same firmware interface for any given macOS version for all socs
<karolherbst>
as long as you don't clock memory, it's not complicated... normall
<karolherbst>
y
<marcan>
also, it's inception
<marcan>
there's a cortex-m3 for realtime stuff
<karolherbst>
uhhh
<marcan>
so there's *two* layers of firmware
<marcan>
the DCP powers that on when the output comes up
<karolherbst>
"fun"
<karolherbst>
one external display really is limited, especially if it sounds like to be such a fake limitation
<marcan>
well, it's only sort-of fake
<marcan>
apple clearly designed these things with two pipes for tiled stuff only, even if you can abuse it for independent displays
<marcan>
the pro machines have a separate DCPEXT, each with two pipes, for every supported monitor output
<marcan>
(2 on M1 Pro, 4 on M1 Max, 8 on M1 Ultra)
<marcan>
it's a waste of hardware though, I agree
<marcan>
on the silicon you can see how each DCP has two mirrored halves
<marcan>
and I guess most of the time only one of those is used
<marcan>
but who knows what Apple HW engineers are thinking...
<karolherbst>
maybe just hope it's only the M1 being stupid and it will be a none problem on future gens?
<marcan>
M2 is the same
<karolherbst>
:(
<marcan>
the DCP is actually *huge*
M152ari[m] has joined #asahi-gpu
<marcan>
er, DISPEXT I mean
<marcan>
I am not surprised they don't throw the silicon at it on the low end SoCs
<marcan>
one DISPEXT is bigger than two PCPU cores
<karolherbst>
I actually saw that one earlier :)
<marcan>
and yes, that's the thing, M1/M2 are ipad socs
<marcan>
apple just put them into the low-end laptops too
<marcan>
a lot of DISPEXT seems to be cache
<karolherbst>
still wondering how much it's doing. It obviously has enough cache for PSR and all that funky stuff
<marcan>
my guess is that they burst large chunks of framebuffer out of RAM at a time, so the RAM can be put to sleep most of the time
<karolherbst>
yeah
<karolherbst>
also
<karolherbst>
changing RAM clocks
<marcan>
I don't think it has enough cache for whole frames, but yeah
<marcan>
that too
<karolherbst>
why not though?
<marcan>
24MB of SRAM for 4K, for each DCPEXT? don't think so
<karolherbst>
mhhh
<marcan>
sorry, bad math, 33MB :)
<karolherbst>
yeah probably just a "line buffer" then
<marcan>
no, I think it's a big fat buffer
<marcan>
like at least 1MB or something
<marcan>
just not the whole frame
<marcan>
so they can burst out big chunks out of RAM, at full speed, then power it down
<karolherbst>
yeah...
<marcan>
which is a lot better than other SoCs that have RAM powered on all the time during scanout
<karolherbst>
but that also means they can turn off the RAM pretty quickly
<karolherbst>
and turn it on
<marcan>
that's not surprising for LPDDR I think
<marcan>
we know the RAM can change perf modes pretty fast too
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<marcan>
this mobile stuff is super optimized for fast power transitions
<lina>
Yeah, the GPU turns on and off in less than 2ms
<lina>
Maybe even less, hard to tell exactly with the firmware power management time slice
<karolherbst>
right.. and this is only about RAM
<karolherbst>
and it might even be good enough to just slow it down
<karolherbst>
or to put it into self refresh
<karolherbst>
well.. obviously it's not powered down completely..
<marcan>
it's mostly about stopping clocks and the IO interface, and yeah self refresh while that's down
<marcan>
it's those 1000+ high-speed IOs that eat all the power
<karolherbst>
yeah.. that should be quick enough
<karolherbst>
cutting clocks is more or less instant
<karolherbst>
link training is what's more annoying
<marcan>
yeah, but once it's trained you keep the same training
<karolherbst>
but on Nvidias kepler gens I achieve 1000 full memory and core clock cycles per second
<karolherbst>
*achieved
<marcan>
you don't have to actually retrain for each power transition, only periodically for temperature compensation
<karolherbst>
wanted to stress test reclocking...
<marcan>
I have the CPU clock latencies somewhere, but IIRC it was like 50µs for slowest to fastest clock, including voltage ramp-up
<karolherbst>
so yeah.. I can see how apple can do that in sup 1ms time
<marcan>
so you do the math for how many CPU clock transitions per second we can do :)
<karolherbst>
yeah...
<karolherbst>
CPU clocks are easy
<karolherbst>
memory is what's annoying
<marcan>
it's the voltage that kills you
<marcan>
downclocking is 5µs
<marcan>
upclocking needs to wait for the voltage to go up
<karolherbst>
right.. but that's still fast
<marcan>
but Apple have really fancy PMUs for that, especially on the pro machines
<marcan>
massively parallel CLVRs right under the SoC
<marcan>
there's 10 of those chips under the M1 Ultra, it's pretty ridiculous
<marcan>
and each has like 20+ power phases
<karolherbst>
nice
<karolherbst>
why is airport wifi...
<marcan>
I think PMGR directly sequences SPMI commands to those when CPU clocks change, no firmware involved
<marcan>
(probably some big table somewhere initialized by iBoot)
<karolherbst>
power phases as in power states?
<marcan>
power phases as in independent switching converters
<karolherbst>
ehhhh.. yeah, that makes more snese
<karolherbst>
*sense
<marcan>
you know, like those motherboards that advertise 8 or 10 power phases on x86
<marcan>
M1 Ultra has 200 or so
<marcan>
:)
<karolherbst>
ahhh right...
<karolherbst>
I've heard about those
<ar>
marcan: but that usually doesn't count the on-cpu converters, and I'd be really surprised if there wasn't some of those there too
<marcan>
Intel has been doing on-package converters on and off lately
<marcan>
I don't think AMD does it?
<karolherbst>
intel....
<marcan>
It's the same concept, Apple just does it on the other side of the motherboard, which isn't that much further away
<karolherbst>
their CPU make loud noises, it's super annoying
<karolherbst>
:P
<karolherbst>
though it's probably not the CPU itself
<marcan>
But it's actually hard to find out exactly what intel CPUs have FIVRs these days
<marcan>
I think only some models do
<karolherbst>
I think I'll be happy I can ditch x86 laptops and get more than 10 hours of battery runtime... :D
<karolherbst>
oh well..
<karolherbst>
I hve no idea if laptops OEMs or Intel or whoever is designing the systems, but when "electrical noise" is what I get when fans actually turn off, I am actually wondering who even designed those systems :(
<juleeandres[m]>
I will tell 20 people how to make $10,000 or more in just 3 days from the cryptocurrency market, but you will pay me 10% commission when you receive your profit. if you are interested send me a direct message, for more information... Contact via telegram
<karolherbst>
though I do know apple harware making those noises as well, but that systems is _old_
juleeandres[m] was banned on #asahi-gpu by marcan [*!*@2001:470:1af1:101::edb0]
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<ar>
i wouldn't mind the m2pro, but in the chassis of a thinkpad x13. I'm really not fond of the keyboard and touchpad on apple devices
* karolherbst
doesn't like thinkpads
<karolherbst>
but mainly because lenovo thinks selling portable jets is a selling point
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<ar>
you mean fan noise?
<karolherbst>
"uhhh CPU reached 60º? let's push the fans to 100%"
<karolherbst>
I actually like my Dell laptop. It doesn't turn the fans on even if the CPU reaches 100£
<karolherbst>
º
<ar>
dunno about intel models; the one i have (with ryzen 4750U) doesn't do that
<karolherbst>
it waits like 5-10 seconds to see if the load goes away
<karolherbst>
ar: yeah... I think only the P1 are actually doing that
<karolherbst>
I have a P1G2 and P1G5 at home
<karolherbst>
both are loud annoying piece of....
<karolherbst>
full burst when booting.. nice...
<karolherbst>
who doesn't want a laptop which cleanrs your flat while installing your distro
<ar>
i think the p50-something i had from a company i worked for 2 years ago was a "fun" one. it managed to be, at the same time, louder and slower than my private laptop…
<karolherbst>
:D
<karolherbst>
yeah.. that sounds like my experience with lenovo
<karolherbst>
the P50 is also of that workstation line
<karolherbst>
those workstation laptops are usually the ones ending up getting RHEL installed on them, so that's why they tend to end up at my place
<karolherbst>
though It hink I also have a T14s3 which is less annoying?
<ar>
then again, i'm happy with my x13; i was happy with the formfactor and battery life of x260 (20 hours of actual non-idle battery life, and one of the batteries is hot-swappable so you could easily extend that…)
<karolherbst>
ehhh t14sg3
<karolherbst>
20 hours is actually quite impressive
<ar>
sadly, the performance of x260 was absymal; dual core low voltage skylake doesn't get you far
<karolherbst>
might explain the battery runtime...
<karolherbst>
only 1.5 more hours to wait :(
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<sven>
marcan: fwiw, if you tell DCP to connect to two streams it already starts some „split av interface“ instead of the normal „av interface“. I kinda expect this to either just crash immediately or actually work
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<karolherbst>
did anybody actually tried any of that or are there only people talking about it :P
<sven>
Ive only gotten DP alt mode output working literally days ago ;)
<karolherbst>
ahh
<sven>
And now I need to port this to a Linux driver because I only have two usb c ports
<sven>
and I need one for my serial connection and then I don’t have enough left for two screens
<sven>
I guess that’s just something like displaylink?
<karolherbst>
not sure
<sven>
that just seem to be custom usb devices that send the framebuffer over sone protocol they made up
<sven>
*some
<karolherbst>
probably..
<jannau>
sven: minimal dcp/iomfb refacoring is in asahi-dcp-october
<sven>
Nice!
<jannau>
I haven't yet split the iomfb members from struct apple_dcp but I've reordered and annotated them
<sven>
sounds good, looks like conflicts should now be minimal if I start with the new endpoints
<jannau>
rtkit endpoint api is one start_ep call and an endpoint specific recv_message callback
<jannau>
do we need synchronisation between the endpoints?
<sven>
I don’t think so
<sven>
They’re pretty independent from what I can tell
<sven>
and at least at one point we need to send a message to dptx and then react to the dpav init messages before we get the dptx reply
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<marcan>
sven: isn't the AV interface one of the EPICs? I doubt the main IOMFB is split
<marcan>
I do expect split EPICs for both sides (so you could poke i2c separately etc) but I don't expect the main IOMFB to be split
<sven>
yes, but it seems to be connected to iomfb so I kinda expect everything to either explode or just work when I connect two separate screens
<marcan>
well, I mean, "just work" in what sense?
<marcan>
if there is only one IOMFB then that needs a tiling config from EDID to make sense of both outputs
<marcan>
if IOMFB really splits in half then that would be interesting
<marcan>
then there has to be some field somewhere for the index though
<marcan>
I didn't see any obvious place for that other than some unused bits in the EP messages
<marcan>
my understanding from strings and such is that IOMFB is shared and the EPICs get split
<marcan>
and IOMFB needs to know about the tiling config to set up two outputs
<sven>
afaict that dpav thing is also shared, it’s just called split interface now
<marcan>
hm, I expected more EPIC instances to show up
<sven>
DCPAVSplitDisplayVideoInterface
<sven>
Let me check again, but I think only that appears
<marcan>
ah, so that's like some shared one that is special for split mode
<marcan>
but you still have separate EPICs for the underlying dptx right?
<sven>
yes, they always exist
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<sven>
hrm, i wonder how it gets the link rate. it needs to know that before setting up ATCPHY
<sven>
can't find anything in that tps6598x datasheet
<sven>
ohh... i think i know what happens. it first just brings up atcphy but doesn't setup the tunables yet, then it routes atcphy to some dcpext and then dcpext calls setLinkRate and only then does it finish setting up atcphy
<marcan>
the link rate would be determined dynamically by the DP negotiation stuff, so that makes sense
<marcan>
I think that happens over the aux channel
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<sven>
yup, that's also how it detects if the display is tiled apparently
<sven>
xnu first just connects dcpdptx-port-epic0, then dcp calls setTiledDisplayHints and then xnu connects dcpdptx-port-epic1
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<alyssa>
sven: brain
<sven>
brain?
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<jannau>
hmm, even simple-panel is too complex to model dcp attached display panels in DT
<jannau>
requires a power supply which I would have to invent out of dcp
<sven>
I‘m not looking forward to model the entire atcphy/crossbar/tps6598x stuff either
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<jannau>
the dp to hdmi bridge is strange as well. it should be modeled to explain hown an (e)dp port can end in an hdmi connector but we do not need to control it
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<marcan>
I don't expect existing DT bindings to be very useful for this, since they're mostly intended for real hardware, not a giant firmware abstraction
<marcan>
we're going to have to cook our own
<marcan>
I think the DP-HDMI bridges should be just child nodes of dcp or wherever they make sense, and just have a compatible (in case we need to start driving them) and say what the right connector type is on the other end
<marcan>
or something like that
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<jannau>
yes, I have now "apple,mcdp2920" as compatible. if we need to drive them it probably isn't via spi or i2c
<marcan>
if we need to drive them it'll be over i2c via the DCP i2c interface, most likely, if not a higher level abstraction, but that doesn't *necessarily* need to go through the i2c subsystem at this point (not the first DRM driver to not do that for bridges)
<sven>
I haven’t found anything that’s even close to the flexibility apple has with the entire typec/thunderbolt/phy/crossbar stuff either
<sven>
there’s just some if the type-c-connector stuff we can reuse
<sven>
*of
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<jannau>
I gave up modeling the display pipeline after DCP, everything assumes components behave like normal hardware. best solution seems to be indeed to stuff the information as property or subnodes into dcp