ChanServ changed the topic of #asahi-gpu to: Asahi Linux: porting Linux to Apple Silicon macs | GPU / 3D graphics stack black-box RE and development (NO binary reversing) | Keep things on topic | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-gpu
<phire>
also max_freq_mhz is missing a divide by 1000000
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<phire>
otherwise all the initdata looks identical to me on my machine (ignoring rel_max_powers and rel_boost_powers)
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<lina>
Ah yeah, my weirdo old mesa for this still had the "force linear" patch in it...
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<phire>
Yeah, suspected as much
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<lina>
jannau: Can you take another dump of the M1 Ultra with that agx trace script, but save the HV log (-l log.txt) and send me that?
<lina>
I want to figure out if any of the few SGX registers read at startup have like a variant/model ID, if I can convince my macOS that I have a lower-core model I can find out if that's really what matters or not
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<jannau>
lina: one moment, I have reboot 2 machines
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<lina>
jannau: Actually, use trace_all (on top of trace_agx) too if you can
<lina>
It'll be a huge log but it might have something useful...
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<lina>
jannau: Actually actually, use hv/trace_all_more.py which I just pushed...
<lina>
I just realized trace_all was untracing pmgr/error_handler which definitely have reg ranges related to fuses in them...
<jannau>
done
<jannau>
not done, I forgot to update the command
<jannau>
updated
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<lina>
jannau: Heh, looking at the SGX registers it reads at the beginning, yours has what looks like a mask of active cores...
<lina>
... and yours are completely regular, so I'm pretty sure Apple is turning cores off for marketing reasons and not yield at this point, at least for you
<lina>
phire: If you get a chance, can you do the same trace? initdata with that pwr script + hv/trace_all_more.py
<jannau>
at this point == since they started shipping. if I have 1 broken core there is a 1/4 chance that it would still look regular
<lina>
True...
<lina>
Though they get to pick both dies, and presumably they would pick two bad ones if they had enough of them
<jannau>
I can do a dump of the m1 max (24 core gpu) if that helps
<lina>
So then both would have to line up, which is a 1/16 chance
<lina>
jannau: Sure! More data is great ^^
<jannau>
but yes, I sure they have more demand for "broken" chips than their yield produces
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<lina>
OK, so at least some things are adding up...
<lina>
The core leakage/static power data is additive. If I subtract f=0 data from f=1000 data, the total power becomes constant
<lina>
So that means there is no per-core shenanigans for dynamic power, and the static and dynamic power are just added together
<lina>
And the f=0 data is proportional (to within the available significant digits) to the leakage table values.
<jannau>
lina: at the same place with the obvious s/8/4/ fix
<jannau>
phire: change line 76 to "for j in range(4):" for the m1 max
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