ChanServ changed the topic of #asahi-gpu to: Asahi Linux: porting Linux to Apple Silicon macs | GPU / 3D graphics stack black-box RE and development (NO binary reversing) | Keep things on topic | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-gpu
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<lina>
So the M1 Ultra just needed a bunch of new buffers and some larger bigger ones, initdata changes, and a couple constants changed, and then it worked.
<lina>
There's a Z acceleration/hierarchical Z thing that showed up, and then 5 new buffers adjacent to the tiler?
<lina>
I get the feeling they're actually trying to balance work within single jobs between dies, which would explain why they need some new buffers to transfer things around.
<lina>
Parallelizing fragment processing is trivial, but fragment is not, since it interacts with the tiler/sorting stuff
<alyssa>
lina: as I texted you, the "Z acceleration" buffer is probably just from depth compression, which Apple's driver is aggressive about enabling and took me a lot of time to figure out how to disable
<alyssa>
it does visually look like hier-z but I'm not convinced it actually is
<lina>
alyssa: I've never seen it enabled on the M1 Mini, ever. I have zero hits for those pointers in all my historical hypervisor logs. But on this one, it showed up, and mesa was faulting without it... so I'm not sure you disabled it ^^
<alyssa>
Very curious
<alyssa>
I'd love to see the Mesa patch if you've pushed
<alyssa>
(the diff from t8103 mesa I mean)
<lina>
Let me do that!
<lina>
The size is just random though, haven't worked out how to calculate any of it yet.
<lina>
The stencil one is just a guess though, haven't actually seen it yet
<lina>
Looks like it's 1/32 compression and it uses POT addressing, so align zbuffer size to POT and divide by 32 for the accel buffer size
<lina>
It seems every 8x4 block of Z pixels maps to one accel buffer byte, 0x03 means clear.
<lina>
Still need to look at the deflake buffer sizes... 2 of them are obvious due to adjacency, but do you remember how you figured out the third bound?
<alyssa>
lina: guess
<alyssa>
or maybe not
<alyssa>
no, adjacency as well
<alyssa>
finding the next allocation in the same BO and using that as an upper bound
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<phire>
I suspect the accleration buffer stuff is just because whatever alyssa did to force a linear buffer, has regressed for some reason
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<alyssa>
s/linear/uncompressed/, IIRC it's stil twiddled
<alyssa>
Metal really doesn't like rendering to linear
<alyssa>
It's probably not a *big* deal to support properly in mesa but that patch is not the way to do it
<phire>
so it's just compressed vs uncompressed?
<alyssa>
Yes, I think so
<jannau>
hah, dcp supports XRGB afterall, just not as separate pixelformat but via a flag in dcp_surface (either unk1 or unk2)
<jannau>
but it took me far too long to realize that fbcon displayed just a transparent terminal