marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-stream #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
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<chadmed>
is this a different patchset to the one already RFCed or just v2 of that patchset
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<marcan>
< sven> looks like macos does a full xhci reset whenever a new device is plugged in fwiw <- smells like a bug
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<marcan>
(hardware bug)
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<sven>
marcan: yup, that's what i assume as well at this point. especially because i can sometimes get it into a weird state if i just reset the PHY
<sven>
easier in device mode where it'll suddenly get spammed with USBReset events
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<marcan>
yay
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<marcan>
maz, kettenis: on the subject of DT properties vs autodiscovery stuff, how do you feel about things that have a "default state" and an "alternate state" described by magic constants? should the DT describe both, or let the driver consider the boot state the default and only describe the alternate?
<marcan>
I'm thinking of the memory controller performance state thing, where macos (and the corellium take on this) apparently just read the registers to determine the default state, and the (A)DT only describes the magic value to replace it with for performance mode
<marcan>
but that seems flimsy in the face of things like kexec or just bootloaders wanting to switch perf modes
<marcan>
to me it would make more sense to describe both states (in an array), but I'd like opinions :)
<j_ey>
is there a need to go into a lower perf state for the memory controller? if you read the current state after a kexec and youre already in the higher state, just do nothing?
<marcan>
the perf state tracks the p-core perf state (at least that's how macos does it)
<marcan>
i.e. when the p-cores are above a threshold, the MCC gets kicked into a higher perf
<marcan>
(that's another question, whether this magic should just be in the cpufreq driver or whether we should describe a separate mcc and split it into a different driver)
<marcan>
(I guess that depends on whether *other* things, like e.g. GPU usage, can trigger this performance state; I should do some tests along those lines...)
<kettenis>
I think the DT should describe all the supported states
<j_ey>
same, can't see a downside to it
<marcan>
since there's one MCC and likely to be multiple p-clusters in the future, that's probably worth considering for architecting this as a separate driver (multiple consumer one producer)
<marcan>
(probably using the genpd stuff at this point)
<marcan>
good excuse to look into that
<chadmed>
probably a worthwhile endeavour to ensure the machine enters a sane state once linux is loaded too if for some reason the driver is being weird. werent you saying just earlier that the default state its in now is weird and suboptimal?
<kettenis>
The way "pstates" are typically represented in the DT is through OPP tables that describe the frequency and the associated voltage
<marcan>
the default state is low perf for the p-cores
<marcan>
I'm considering bumping that to at least 2GHz in m1n1 on SMP startup, just so that if another OS without cpufreq gets loaded it gets at least some reasonable performance
<marcan>
kettenis: yeah, I saw that, for CPUs at least
<marcan>
I intend to do it that way
<kettenis>
they also get used for GPU and memory controllers
<marcan>
but I don't know how to tie that in with the memory controller; I also saw the genpd stuff can describe things like voltage requirements IIRC
<chadmed>
kettenis: thats common for all DVFS capable devices isnt it
<kettenis>
but I'm not sure there is a mechanism to describe dependencies
<marcan>
ah, makes sense to use that then
<marcan>
yeah, genpd should be able to do that but I don't know if it uses the OPP stuff or something else
* marcan
wonders if there's some way to figure out what these magic values actually mean
<kettenis>
not sure the standard OPP tables would work
<kettenis>
don't think they allow encoding magic register values
<marcan>
fwiw, for the CPU the actual hardware interface is just a pstate index
<marcan>
so OPP tables work for that in that I'd just use the state index
<marcan>
but for the memory controller, yeah, I need magic values
<kettenis>
I fear the default way existing platforms handle that is by putting the magic values in the driver
<kettenis>
but I guess that's what you want to avoid
<marcan>
ideally yes, to make this more likely to work on other platforms
<marcan>
though we're kind of guessing here, since this is the first device of its class
<marcan>
maybe I should look at some iOS ADTs and compare... that might give us some good hints of what to expect
<kettenis>
maybe it isn't too bad to rely on the driver here
<marcan>
might be
<marcan>
main thing is if these ever vary between devices for a single SoC
<marcan>
then we really need DT properties
<kettenis>
if m1n1 puts things in a reasonable state, Linux would still run if this stuff doesn't work on a new machine
<marcan>
yeah, of course
<sven>
more usb fun: doing the full phy reset sequence macos does put the dwc core back into device mode even it was in host mode. looks like we'll actually have to tear down xhci and start it back up again whenever something is hotplugged :( (luckily that's like 10 lines changed in the linux dwc3 driver, but ugh)
<chadmed>
that seems like a pretty bad bug to leave in silicon. but i guess if no one outside of apple was ever meant to discover that it exists they can get away with it
<kettenis>
sven: wonder how I'm going to implement *that* in OpenBSD
<sven>
yeah. it's ugly :(
<sven>
i can hack this in linux because dwc3 as dual role support and already supports reinitializing the entire thing when transitioning from host -> device
<sven>
so we can kind abuse that path to also do it for host -> none -> host transitions
<sven>
that's where it switched back from device to host
<kettenis>
svan: you mentioned resetting the PHY is really broken in device mode, but even in host mode that doesn't work reliably?
<kettenis>
s/svan/sven/
<sven>
it works most of the time
<sven>
but sometimes it then starts detecting a new device every ~5s or so
<sven>
[ 5.547529] usb 3-1: new high-speed USB device number 3 using xhci-hcd
<sven>
[ 11.404222] usb 3-1: new high-speed USB device number 4 using xhci-hcd
<sven>
^-- like that
<kettenis>
fun
<sven>
it's just easier to reproduce in device mode because i have driver for that in m1n1
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<marcan>
looks like all M1 *and* A14 devices use at least the same MCC performance mode setting
<dottedmag>
sven: So plugging a USB memory stick will cause USB-connected keyboard/mouse to disappear and reappear?
<marcan>
dottedmag: you can't plug two things into one port
<sven>
dottedmag: no. it won't recognize any device
<sven>
it just starts printing "new device" every 5s or so
<sven>
it's broken at that point
<marcan>
it's one dwc3 controller per type C port AIUI
<sven>
oh. yes.
<dottedmag>
sven: I mean, if a full reset is required
<marcan>
hubs don't count
<sven>
yeah
<dottedmag>
marcan: Ah, ok
<sven>
what's weird though: if you put a usb-c -> usb-a adapter inbetween reconnecting the usb-a side works just fine
<marcan>
it's clearly something to do with the PD chip
<sven>
that's certainly what mac os uses to trigger the reinitialization
<marcan>
which is why this is weird
<dottedmag>
So a single controller per type-C port is why nobody noticed it under macOS, right?
<sven>
macos works fine
<kettenis>
ah, there is required-opps to encode dependencies between OPP table nodes
<marcan>
like why would dwc/the phy care about what the PD controller does
<marcan>
unless it does something dodgy with D+/D-
<sven>
i suspect it *may* be possible to just manually inject a "new device connected" into xhci to make this work
<sven>
but ugh.
<marcan>
but why
<sven>
no idea. this whole thing makes no sense to me
<marcan>
I don't really get why this happens at this point
<sven>
me neither :/
<marcan>
should I place an order for another Mini for victim purposes? maybe it's time to bring out the oscilloscope...
<sven>
my best guess that it's something in the PHY that goes wrong
<sven>
but i have no clue what that might be
<marcan>
yeah, but the thing is... if you do a type A reconnect, the PD controller does not notice
<marcan>
however, if "whatever" the PD controller is doing on the PD lines can wedge the PHY... then an external device can also do that
<j_ey>
marcan: <sven> and maybe get marcan to hook up a oscilloscope to the i2c bus to figure out what that 800 bit does
<marcan>
then you end up with a situation where you can wedge a type A adapter and need to reconnect the type C side
<j_ey>
marcan: just saying :p
<marcan>
j_ey: I don't need a new mini for the i2c bus
<marcan>
that's aleready exposed on debug pins on the typ c
<sven>
the "half broken xhci/dwc" state is probably just because i do a partial PHY reset
<marcan>
*type c
<marcan>
sure
<marcan>
but then why is a reset needed *at all*
<sven>
yeah, that's what's so strange
<sven>
i think it might be possible to do without a reset by manually faking the "new device" event in xhci
<j_ey>
marcan: ah, makes sense
<marcan>
would be really nice if an M1 schematic leaks at some point :p
<sven>
or if apple just published "ATC PHY Technical Reference Manual.pdf" :p
<marcan>
lol
<chadmed>
that would be a good april fools
<jn>
M1 board schematics, or module schematics, or chip HDL?
<chadmed>
Apple commits to Open Hardware movement, publishes Verilog for all SIP
<alyssa>
sven: TBH if macOS does the full reset and Linux is broken without it... then do the full reset, no good way around that
<sven>
sure, that already works
<sven>
but i want to understand _why_
<sven>
and if it's possible to do this in a saner way
<marcan>
jn: board schematics
<marcan>
iPhone/Mac schematics all tend to leak at some point, it's the only way people can repair these things
<marcan>
alyssa: remember we're trying to do better than macos here ;)
<marcan>
e.g. on the cpu pstate stuff, corellium does a bunch of useless stuff, macos does a subset of it that seems to be vestigial, what is actually required is even less
<marcan>
so it's worth figuring out what we don't need to do
<marcan>
and yeah, I don't see anything in there that explains this USB mess
<marcan>
screw it, I'll order another Mini to take apart
<marcan>
there's at least some chokes used for the lines between the soc and the PD controller, so I should be able to get at the lines
<j_ey>
marcan: plss stream that
<marcan>
:)
<marcan>
You’re . . . early.
<marcan>
Pre-order begins at 5:00 a.m. PDT. Enjoy the extra sleep.
<marcan>
.... what?
<j_ey>
new iPhones
<marcan>
they locked down the whole store
<marcan>
sigh
<j_ey>
they turn the site off
<j_ey>
lol
<chadmed>
yeah ikr
<j_ey>
just nip out to the nearest apple store
<sven>
lol
<marcan>
it's 9PM :p
<marcan>
but yeah I might just drop by somewhere tomorrow
<chadmed>
"10:00 PM AEST" its that now, apple whats the hold up
<mini>
"Just a few finishing touches" now...
<sven>
if you want to hook up something to an oscilloscope anyway: would also be nice to figure out what bit 0x800 in REG_CTL of the i2c controller does :>
<sven>
(without that i can't talk to the PD chip)
<chadmed>
so stupid, they should know my iphone x does not need replacing... yet
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<marcan>
meh, amazon has it
<marcan>
sven: sure
<marcan>
*click* ordered
<sven>
:)
<marcan>
honestly, 9 months has been way too long to not bring out a screwdriver
<sven>
if you need extra motivation: once i know what that bit does i can probably submit the first version of the i2c driver
<marcan>
my guess is enable clock stretching
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<marcan>
but I can also look at that via the debug port
<marcan>
just need to plug in my glasgow again :>
<sven>
sure
<marcan>
sven: wait, m1n1 doesn't set that bit?
<marcan>
is this why it's unreliable for some people?
<sven>
no
<sven>
that bit is already set there
<marcan>
ah
<sven>
iirc i only use set32/clear32 in the driver
<marcan>
yes
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<sven>
yeah, that's why it works. i originally didn't know why it broke when i used write32 :D
<marcan>
:D
<sven>
macos checks some other register and only sets that bit if that other register is >= 6 or so
<marcan>
huh
<marcan>
version?
<kettenis>
smells like it
<sven>
0x28
<kettenis>
maybe they still have code to support the original pasemi chips
<sven>
which is REG_REV in the corellium driver
<marcan>
kettenis: those are PCI, so unlikely
<marcan>
but they probably had some prior revision of this IP
<marcan>
the old pasemi docs do mention supporting clock stretching (with a timeout)
<marcan>
could also be a clock select
<kettenis>
ah, apparently systemd is in the EFI bootloader game now as well
<chadmed>
hasnt lennart been spruiking that for a while at this point?
<chadmed>
ive been hearing about something like that for more than a few months
<chadmed>
the year is 2045 and there is now fixed function systemd hardware on all socs
<psykose>
systemd-boot has existed for years
<psykose>
unless it's something new
<marcan>
sven: the i2c controller doesn't run at all with that 0x800 bit clear
<marcan>
the fifo stays full, transaction doesn't even go into the start stage
<marcan>
sounds like a clock select or somesuch, where the default is not active
<marcan>
you can start a transaction, see nothing happen, set the bit, and it goes through
<sven>
hrm. okay. guess i'll just duplicate the if (hw_rev >= 6) logic then
<sven>
thanks
<marcan>
perhaps even a general "enable" bit
<marcan>
I guess we can treat it as that
<sven>
yeah
<marcan>
also btw, the original pasemi chips do not have the revision register
<marcan>
so only do that thing for the DT/platform dev version
<sven>
alright, good to know
<kettenis>
does macos just set that bit and leave it on?
<kettenis>
or does it set and clear it around transactions?
<sven>
there's another bit it sets and clears around transactions
<marcan>
which one?
<kettenis>
the "enable" bit
<kettenis>
0x800
<marcan>
the othe bit
<sven>
0x44
<marcan>
offset?
<sven>
sorry :)
<sven>
register 0x44, BIT(0)
<marcan>
that's also not a thing on pasemi
<marcan>
(nothing >24 is)
<sven>
it also doesn't seem to make a difference
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<sven>
macos sets that before it starts a transaction and clears it afterwards iirc
<marcan>
setting that bit also stops everything
<marcan>
sounds like you have it backwards
<sven>
no
<marcan>
I just tried setting that in m1n1 and it broke everything :)
<sven>
did you clear it again after the transaction?
<sven>
or, well, after writing to the fifo i think
<marcan>
well yes, once I clear it it works again
<sven>
yeah. so for some reason it does that
<marcan>
so it sounds like another halt bit
<marcan>
it makes sense though
<marcan>
the transmitter can time out on you if you don't fill the fifo fast enough
<marcan>
so this allows you to fill it then burst everything out
<sven>
ah, makes sense
<marcan>
as long as the whole txn fits in the fifo
<marcan>
wonder how big the fifo is
<marcan>
pasemi says 16 bytes
<marcan>
maybe this does more
<sven>
probably not required for the initial merge. you can always add it together with interrupt support later :>
<marcan>
oh yes it does
<marcan>
128 byte fifo
<marcan>
cool
<sven>
that's actualy quite useful. the transactions to the PD chip are always less than 65 byte iirc
<marcan>
yeah, probably why they did this
<marcan>
it means you don't care if you get preempted in the middle of this driver
<sven>
yeah
<sven>
hm. i wonder if the first non-pci controller just has revision = 1
<sven>
we could just pretend pci is always revision = 0 then
<marcan>
or call it -1
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<sven>
ah, true. that would work as well
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<alyssa>
is booting the M1 to do theoretical CS homework overkill?
<alyssa>
nahhhhh
<alyssa>
need to, err, test maz's PCIe patches harder, mmhmm
<bfredl[m]>
procrastination-driven-development is standard (basically how the entire julia language was done :)
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<ar>
alyssa: just watched your xdc presentation, and I think it was great. there's just one question that's probably somewhat naive: what's the advantage of making a dedicated opengl implementation, instead of doing just vulkan and relying on zink?
<i509vcb[m]>
I imagine zink relies on some vulkan extensions being implemented
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<i509vcb[m]>
unsure on the exact extension surface
<i509vcb[m]>
I think both OpenGL and Vulkan are about as equally wordy and long
<i509vcb[m]>
OpenGL probably has more people experienced with implementing it also
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<alyssa>
ar: at this stage, the asahi gallium driver is gles2-only, is mostly copypasted from other drivers, and mainly exists as a way to test the compiler :)
<alyssa>
and... i know gallium/opengles intimately, i don't know vk quite so well. for copypasting together something for some demos, gles2 was the easy ovbious easy
<alyssa>
vulkan would be lovely..
<i509vcb[m]>
Vulkan covers a level of abstraction close to gallium, so I think you'd need to do vulkan mostly from the low level
<alyssa>
vulkan is probably easier tbh
<alyssa>
gallium requires some backflips if you care about performance
<i509vcb[m]>
Vulkan also has quite a detailed spec and lots of validation tests
<j_ey>
sven: missing sign off dd705fce678e72700b6ed97334864e9af6e1be3f
<sven>
ah, whoops.
<sven>
fixed, thanks.
<j_ey>
is "hack: allow to compile pasemi pci driver without pasemi" new, I dont remember seeing it before
<sven>
yeah
<sven>
just wanted to make sure the pci driver still compiles
<sven>
(also hopefully also get the kernel builder bots to pick it up and see if i broke anything)
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<j_ey>
ah
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<alyssa>
sven: "HACK/DONOTMERGETHIS" what's wrong with the DT again?
<sven>
uh, it works fine that way but i'm not sure about how the usb phy will be connected to that yet. it also needs to be split into separate commits
<alyssa>
gotcha
<j_ey>
and is probably going in separately to the driver code anyway
<sven>
yeah
<alyssa>
👍
<sven>
this will all be "fun" anyway. those driver changes will go through at least two separate tree. possibly three if I get the PHY driver ready for usb3
<sven>
oh, it's already three thanks to pinctrl :D
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<alyssa>
sometimes the kernel feels "too big"
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<sven>
this is still okay because only the dt change depends on all of them. rtkit will be interesting.
<sven>
rtkit itself will depend on the mailbox code. and then nvme and dcp and smc all depend on rtkit
<sven>
not impossible to handle all that, but that will require some coordination if it all goes into the same merge window
<j_ey>
how do drivers/soc commits get merged?
<sven>
same way the initial bringup did - through the soc tree i think
<alyssa>
sven: what has to happen for mbox+rtkit to get merged at this point?
<sven>
mbox needs to be reviewed by the mailbox maintainer first
<alyssa>
alright
<sven>
rtkit.. dunno... i guess i'd first need to submit it together with something that uses it? :P
<alyssa>
nod
<alyssa>
smc is probably the easiest user?
<alyssa>
do you still need smc for type-c stuff, I guess not then?
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<sven>
nope
<sven>
for that i "just" need i2c, the patches to tipd and the quirk to dwc3 (or a better solution if we find one)
<sven>
ugh. and pinctrl
<alyssa>
fun
<sven>
i keep forgetting pinctrl/gpio
<alyssa>
pinctrl was already needed for pcie..
<sven>
right, but for pcie i can kinda ignore the pinctrl part and it'll still work
<sven>
for the tipd i need the gpio interrupt
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<sven>
(unless you prefer my kthread that just calls the interrupt handler every second or so 😋)
<j_ey>
now that sven has tested with interrupts i2c, to get more coverage, i think its basically ready to send out a v1 of pinctrl
<j_ey>
(and I know the maintainer is interested in it..)
<ar>
alyssa,i509vcb[m]: thanks, that explains it :)
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<sven>
j_ey: time to submit it then :>
<j_ey>
sven: I will try finalise it for next week!