ChanServ changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | "Does XXX work yet?": https://alx.sh/fs | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-alt #asahi-stream #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
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<j`ey>
so the other day I said how m2+linux+wine made my computer hot, but m1+macos+wine didn't.. well I made the m1 use the same third-party ddraw.dll replacement, and it gets hot too
<j`ey>
so, expected, and nothing to worry about too much
<j`ey>
that's when doing 1k+ fps, so probably if I limit it to 500fps or something, it will run cool(er)
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<reverser>
Hi, it's me again. How would I flush the data cache from an Apple M1 under Asahi linux? I am trying to empty my data cache as part of a hardware reverse engineering effort. However, when using the DC CIVAC instruction or the flush_cache_mm() kernel function: both do not seem to have any effect on the content of my data cache? Anything I am overseeing?
<jn>
reverser: which cache level(s)?
<jn>
(just curious. i probably won't have answers to your question)
<reverser>
I am looking at L1 and L2
<reverser>
I am able to evict data via eviction sets, but that approach is a bit slow. I am trying to speed things up by forcing a flush (as clflush does on Intel)
<jn>
how do you check the data cache content?
<Calandracas_>
are any apple silicon devices numa?
<reverser>
I am using a PMU to time how long it takes to access a specific memory address. If the access is below a threshold, the data is stored in the cache.
<reverser>
And Calandracas_: Not sure.
<reverser>
And even when I am trying to flush or use the data cache management instructions (DC CIVAC), I do not see any changes in cache timings. However, I do see a change in timings when "flushing" the memory address by using an eviction set.
<reverser>
(Just accessing a bunch of addresses that have to share the space with my target memory address and cause the target address to be evicted from the cache)
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