#dri-devel on 2022-06-15 — irc logs at oftc.irclog.whitequark.org

2022-03-22 11:57 ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar

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07:18 <MrCooper> linkmauve: git doesn't fetch merge request refs by default, only if explicitly configured on the client side

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13:46 <MrCooper> could somebody add ofourdan to mesa/mesa as a reporter? (Is that sufficient for moving issues there from other projects?)

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13:48 <daniels> I think you can still move issues with /move mesa/mesa as a comment

13:48 <daniels> rather than using the UI

13:48 <daniels> but yeah, added him now

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14:04 <MrCooper> thanks!

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15:44 <robclark> danvet, random thought.. I wonder if it would make sense to register multiple shrinkers with different `seeks` values.. ie. purgeable things don't really need any i/o to discard, so we should handle those thru a lower cost shrinker

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15:47 <danvet> robclark, hm yeah maybe?

15:48 <danvet> but I'm not sure how much that all takes into account

15:48 <danvet> I think it's just some balancing value, and I guess we could fake that internally by adjusting count

15:48 <danvet> like count non-purgeable double

15:49 <robclark> AFAICT do_shrink_slab() will set nr_to_scan more aggressively for seeks==0..

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15:50 <robclark> anyways, was thinking to play around with that.. at least if I could stop finding bugs to fix

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16:43 <tzimmermann> danvet, airlied, last week's PR for drm-misc-next hasn't been merged yet, so I'm leaving out the one for this week

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16:51 <TimothyAlexis> ok

17:08 <danvet> tzimmermann, hm I guess airlied slacking

17:09 <danvet> I'll roll forward to -rc2 and take a look

17:09 <danvet> ah it's already -rc2

17:09 <tzimmermann> danvet, we have holiday tomorrow. so i won't get to send it until friday morning CEST

17:09 <tzimmermann> that might be too late already

17:10 <Lyude> pq: Lol, will inform greg of the reality :P

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17:39 <airlied> yeah me slacking, i rolled fwd but then forgot to process next pull

17:39 <airlied> will do it in next few hrs

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17:45 <danvet> airlied, already compile testing, so get back to slacking :-)

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17:52 <Kayden> MrCooper: added ofourdan to mesa overall as a reporter

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18:14 <danvet> tzimmermann, pr merged&pushed

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18:18 * alyssa runs shader-db for the i2b MR

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18:37 <pepp> idr, anholt: I added a comment to https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16662 (yuyv/uyvy MR) - did you see it and do you have any idea of what might cause the failures found by the CI?

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18:45 <demarchi> tzimmermann: did you have a chance to look at the second version of the iosys-map refactor I sent? https://patchwork.freedesktop.org/series/105011/ (I had already sent that before your feedback on v1)

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18:56 <idr> pepp: I'm sure I just need to update Intel drivers to account for the changed ordering.

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19:13 <pepp> idr: ok. Do you want to push the fix to the MR's branch? Or should I update the expected results and mark the test as failing?

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19:23 <airlied> danvet: thx!

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19:26 <idr> I hate all of this yuv shit. It should die in a fire.

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19:31 <zmike> dcbaker: I've got a lot of backports in the pipeline, ping me if any of them don't apply cleanly (I expect there to be a couple)

19:32 <dcbaker> zmike: there’s a couple, but I’m working out some regressions first

19:32 <zmike> cool

19:33 <idr> pepp: There was an issue submitted about this, and I'm trying to find it.

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19:35 <idr> Hm... it was https://gitlab.freedesktop.org/mesa/mesa/-/issues/5528, and it's similar but different?

19:39 <pepp> idr: hmm.. these format mappings are really confusing

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19:39 <idr> And it doesn't help that there's 12 names for the identical format and 13 similar names for different formats.

19:44 <idr> pepp: What PIPE_FORMAT_ are you getting for that surface?

19:45 <idr> My guess is that there's something amiss with how we're mapping PIPE_FORMATs to ISL_FORMATs, but I'm not seeing it. :(

19:51 <pepp> idr: r8g8_unorm from piglit_create_dma_buf, and r8g8_r8b8_unorm from egl_image_for_dma_buf_fd (for the yuyv test case)

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20:05 <idr> pepp: I have a patch that I'm running through the Intel CI.

20:05 <idr> https://gitlab.freedesktop.org/idr/mesa/-/commits/mesa-radeonsi_tests_fixes

20:05 <idr> I have to take off for a bit, but I'll be back in a couple hours.

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20:06 <pepp> idr: thanks! I'll look at the results tomorrow

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20:58 <Sachiel> gee... now that the zink-anv job is using zink instead of iris it runs so much slower...

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21:01 <zmike> T R I G G E R E D

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21:04 <X512> Just for interest, why Zink may be slower? CPU overhead?

21:06 <Sachiel> oh, I don't have any data for that, I was just being an ass

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21:32 <kisak> in case anyone cares, it now appears that the NVIDIA proprietary driver has gotten better about the scenario where the user hasn't installed NVIDIA's 32 bit userspace libraries. It now allows for the OpenGL context to fallthrough to llvmpipe.

21:34 <kisak> Separately, we've got https://github.com/ValveSoftware/steam-for-linux/issues/8555 where X is running on the NVIDIA gpu, and steam starting on Intel causes the user session to crash back to login.

21:35 <kisak> probably libcef + iris + X on NVIDIA

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