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<karolherbst>
robclark: but I suspect there is other hw which works in a simlar way, so maybe it's a good idea to support something like that in a more explicit way
<karolherbst>
and I suspect parsing all exprs form all overrides to figure out if any of them is always hit, is kind of super annoying to figure out
<robclark>
yeah, it probably isn't possible to figure out in the general case
<karolherbst>
anyway.. thanks for your help so far. Already looks better, and I might be able to start dumping the entire ISA now... some other instructions are a bit special, but that shouldn't be too painful
<karolherbst>
the only other thing I can think of which could make it easier is to be able to sae <assert ref="SOME_NAME">11111111</assert> so we can assert on fields directly and not having to duplicate the location (also.. easier to understand probably on why that assert is there)
<robclark>
cool.. maybe dump your ideas for changes/enhancements into a gitlab ticket w/ some examples of what you think the xml would look like.. I think Kayden also had some rough ideas too
<robclark>
(since irc isn't really the best way to track things :-P)
<karolherbst>
robclark: one thing I am not quite sure how to express is, I need to disallow modes 2 and 3 for 2 source alus
<karolherbst>
uhm.. and 7
<karolherbst>
maybe I just put an <assert>111111111111111111111111111111111111111111111</assert> in overrides in #fp_instruction2 ....
<karolherbst>
(actually that shoulve be alu2 and 3)
<karolherbst>
uhm.. guess not, because of FPU stuff
<robclark>
one thing you can do is derived fields in the derived bitset.. look at "getsize" for ex in ir3-cat3.xml
<robclark>
cat5 has a bunch of instructions which have different # of srcs, etc..
<karolherbst>
mhhh
<karolherbst>
ohh
<karolherbst>
didn't know about that expr field
<robclark>
yeah, you can name exrp's if you need to use them in multiple places
<karolherbst>
ahh
<karolherbst>
could probably define a NUM_SRCS in fpu_instruction 2/3 and add exprs for that in alu_instruction
<robclark>
right
<karolherbst>
mhh
<karolherbst>
asserting on those fields would be even more convenient
<karolherbst>
<assert ref="NUM_SRCS">11</assert>
<karolherbst>
or do a <assert ref="NUM_SRCS" val="3"/> thing
<karolherbst>
but that sounds like a bit more work actually
<robclark>
is NUM_SRCS actually a field in the instruction? For us it isn't, it is just a property of the instruction
<karolherbst>
no, it's not
<karolherbst>
just want to make sure the 3 source modes aren't used for 2 source instructions
<robclark>
oh, but FORM is real field and it kinda implies the # of srcs?
<karolherbst>
without that being too nasty (or splitting things into multple fields)
<karolherbst>
no, it's more like depending on the amount of instructions, you can use the three source modes or not
<karolherbst>
which makes sense, but I suspect the hw also complains if you actually try it
<karolherbst>
I also could have an #alu_instruction3 extending #alu_instruction2 and just adding those modes
<karolherbst>
but I also want #alu_instruction2 to assert on those not being used
<karolherbst>
could make it part of the expr, but then I also need the {NUM_SRC} != 3 case and somehow add there a assert on random bits
<robclark>
it might not be unreasonable to have something like <assert field="FOO">111</assert> (so it can work on derived fields) instead of low/high bit positions?
<karolherbst>
yeah
<karolherbst>
I think that also has the benefit of being more self explanatory
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<karolherbst>
uhh...
<karolherbst>
FADD is src0 + src2...
<HdkR>
Of course
<HdkR>
Because it is just an fmadd without the multiply :P
<karolherbst>
well.. hard wired 1.0
<HdkR>
Right
<karolherbst>
HdkR: ohh I was wondering about FMUL32I, is that a mul with src0 as an int?
<HdkR>
I thought that was just an FMUL where you encode a float in the 32-bit constant immediate encoding space
<HdkR>
But maybe, I can't remember tiny things like that :P
<karolherbst>
but well.. they have a proper FMUL instruction...
<karolherbst>
huh.. FFMA32I allows mods on src0...
<karolherbst>
well... _maybe_ but the normal ones also have that...
<karolherbst>
the only diference I see is that FFMA32I can't have a rounding mode
<karolherbst>
so there is a FFMA form with an imm32 _and_ FFMA32I
<karolherbst>
and FMUL32I can't have mods
<karolherbst>
maybe it's faster and that's why is a special instruction.. who knows
<karolherbst>
or maybe it can use the integer ALU...
<karolherbst>
which would be weird
<karolherbst>
oh well..
<karolherbst>
I'll figure it out later
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<karolherbst>
HdkR: this FADD is even more annoying than I thought.. so the pure GPR are form is src0 + src1, execept all the others
<karolherbst>
now how does that make any sense
<karolherbst>
mhhh
<karolherbst>
seems like other instructions only use SRC1
<karolherbst>
e.g.
<karolherbst>
okay.. another problem to figure out
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<karolherbst>
we have a tanh instruction :D
<karolherbst>
is there any API besides CL/CUDA who would be interested?