ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<karolherbst>
robclark: yeah... or maybe to the "specialization", you define a base type with fields and subtypes can overwrite those with values
<karolherbst>
with volta+ everything is really at a fixed position, order is just somtimes different
<karolherbst>
like SRC0 might be at 24 or at 32
<karolherbst>
there is a third position
<karolherbst>
but anyway
<karolherbst>
I'd like to declare a "base structure" for instructions and then say "this specialization has this field always set to ff or 0 or whatever
<karolherbst>
or maybe it's enough to add a <spec name="SRC1">0xff</spec> thing
<karolherbst>
dunno, never looked at the code
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<robclark>
karolherbst: yeah, I think something like that could be done... All the inheritance stuff is done in the py and doesn't really effect the generated code
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<karolherbst>
robclark: okay.. I'll see if I can figure out something nicely
<alyssa>
Oh it thinks that _coefficient registers_ is a link
<alyssa>
isn't that how you do italics?
<alyssa>
no wait that's *italics*
<alyssa>
ok i see what it doesn't like
<alyssa>
extremely confusing error msg though
<emersion>
sphinx is extremely confusing in general :S
<alyssa>
yeah...
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<alyssa>
rosenzweig.io is a pile of markdown files, pandoc, and duct tape. it works :S
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<alyssa>
isl doesn't build on arm64 (-:
<alyssa>
If only I had a DG1 card, I could complain about that (:
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<pjakobsson>
danvet, thanks. Yes it's been a while since someone looked at a Poulsbo kernel log :)
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<karolherbst>
robclark: seems like I can get something close with the existing code already...
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<karolherbst>
mhh
<karolherbst>
can't override pattern though
<robclark>
yeah, pattern is the one thing you can't override, because it needs to know the pattern to match bitset before it starts considering overrides
<karolherbst>
yeah...
<karolherbst>
but besides that it already looks abit better
<robclark>
I guess the alternative would be allow multiple patterns.. but that expands the search space..
<robclark>
(side note.. it occurs to me that I should write some unit tests for isaspec)
<karolherbst>
I kind of like this way better than having multiple bitsets
<karolherbst>
but I think I want a shortcut thing
<robclark>
ok.. will look in a bit.. but breakfast is calling..
<karolherbst>
instead of placing a pattern at a location, allow it to just provide a value for a field
<karolherbst>
doing the same internally, but helping with declaring
<karolherbst>
like instead of "<pattern low="76" high="76">0</pattern>" do "<pattern field=PATCH>0</pattern>"
<karolherbst>
and same for field, just allow the low/high/pos thing to be dropped while inside override and just take the info from the provided name
<karolherbst>
and make sure it matches with the type
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<jekstrand>
dcbaker, jenatali: Do either of you know if anyone is building Mesa with C++17 or higher yet?
<jenatali>
jekstrand: pretty sure we require C++17
<jekstrand>
Looks like freedreno does, pps, and an intel tool.
<jekstrand>
And EGL for some reason?!?
<jenatali>
EGL has C++?
<jenatali>
jekstrand: What's the context? Just curious :)
<jekstrand>
FOr haiku and Android
<dcbaker>
Perfetto requires it iirc
<jekstrand>
jenatali: I want to have something that's built in CI that uses std::has_unique_object_representations
<dcbaker>
I think llvm 15 might as well
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<jekstrand>
So we can compile-fail if structs aren't hashable.
<jenatali>
Ahh I forgot about the Android stuff, yeah
<jenatali>
But yeah, at least from the Windows/MSVC side we were actually close to using C++20 for Dozen
<jenatali>
For the designated initializers so that more C code could build as C++
<jekstrand>
+1
<jekstrand>
We could also just have a build test that runs pahole, I guess.
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<jekstrand>
anholt_: Do we have pahole on the CI builders?
<daniels>
jekstrand: you can add whatever you like!
<jekstrand>
daniels: Yeah, but that requires figuring out docker again. :-(
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<jenatali>
jekstrand: Isn't just a matter of adding it to the container build script (along with all the other dependencies) and then just bumping the container tag?
<jekstrand>
jenatali: Yeah, I think so.
<daniels>
correct
<jekstrand>
Maybe I'll make bbrezillon do it as part of !17186. :-P
<jenatali>
Doesn't sound like figuring out docker to me :P
<daniels>
the tags are in .gitlab-ci/image-tags.yml, the builds are in .gitlab-ci/container/*.sh
<jenatali>
Sure, spend our money on it lol
<daniels>
jekstrand: think of it as personal growth
<jekstrand>
lol
<alyssa>
jekstrand: do we have versions of *_global with constant offsets?
<jekstrand>
alyssa: Not really.
<alyssa>
otherwise I'd have to chase the arithmetic thru in the backend, although I guess ssa_scalar might make that reasonable
<alyssa>
contingent on not lowering iadd64 which I probably should do anyway...
<jekstrand>
alyssa: What are you looking for? 64bit base + offset?
<alyssa>
Yeah
<alyssa>
small constant offset
<jekstrand>
I made versions of global_constant which do that
<alyssa>
that's global_constant + offset, not global + constant_offset, right?
<jekstrand>
it's load_global_constant with 64bit_base+32bit_offset and you can then use nir_src_is_const() to figure out if the offset is constant. Otherwise, you have to add.
<jekstrand>
IIRC, I get rid of all the non-constant offset versions in an ANV-specific NIR pass.
<jekstrand>
It's kinda clunky but keeps everything in a standard(ish) lowering flow.
<jekstrand>
But for Intel, it's really important to know that the 64-bit base pointer is 32B-aligned
<jekstrand>
We turn UBO pulls into 32B block loads whenever possible and those have alignment requirements.
<jekstrand>
s/We turn/Intel turns/
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<alyssa>
all your base are belong to us now (-:
<alyssa>
all your offset are still Intel
<jekstrand>
:P
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<kisak>
I'm starting to get the opinion that AMDVLK should be blocked from the ecosystem until they can co-exist with others
<alyssa>
got regular iadd64 working on valhall
<alyssa>
unlike bifrost v7, valhall restores sane 64-bit support
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<FLHerne>
kisak: What would 'blocking' them even entail, given it's out-of-tree and not packaged by most distros?
<MrCooper>
kisak: co-exist in what way?
<kisak>
I'm just being momentarily grumpy, and it would probably be a vulkan loader patch. Just a little irritated that they break mesa/ANV and NVIDIA on non-AMDGPU systems, and now they've got https://github.com/GPUOpen-Drivers/AMDVLK/issues/278 breaking wine/Proton.
<jekstrand>
Yeah, IIRC they blew up Windows with some of those bugs too. (-:
<kisak>
want to run mesa/RADV with AMDVLK v-2022.Q2.3 installed? VK_ICD_FILENAMES the RADV icds or it's dead.
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<alyssa>
kisak: Delightful
<alyssa>
jekstrand: Now that I don't lower iadd64 in NIR, it's easy to chase out the constant offset with ssa_scalar
<alyssa>
so I don't need any unusual NIR to get the opt I want :)
<jekstrand>
:)
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<alyssa>
instruction count reduced by 58% on dEQP-GLES31.functional.ssbo.layout.basic_unsized_array.std140.row_major_mat3x4
<alyssa>
and 64% on the notorious dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.36
<alyssa>
(which reduces the compile time for that test substantially, way less for RA to deal with)
<alyssa>
In theory the extra ALU around load/store ops doesn't matter since we have piles of ALU and not much load/store bandwidth
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<alyssa>
In practice, such a dramatic reduction of instruction count is going to help i-cache hit rates for compute kernels.
<alyssa>
(the std140 test there fits into the i-cache after but not before, for ex)
<jekstrand>
kisak: I've passed it along to some AMD folks.
<jekstrand>
kisak: They promised to ring internal alarm bells
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<kisak>
jekstrand: thanks, I probably should have found a more appropreate channel to grumble anyway.
<jekstrand>
kisak: No worries. Happy to.
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<agd5f>
OMG. fuck the kernel mailmap. I just spent an hour thinking I was losing my mind
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<karolherbst>
robclark: okay... I think I have a better picture now on what I actually need. changing some bits meaning based on flips looks easy enough, what I essentially just need are some constraints. And not in a sense of pattern matching, but rather runtime validation and not emiting wrong things
<karolherbst>
anyway.. it's probably too early now to prototype this, but I think I can figure out how that should look like in isaspec
<robclark>
karolherbst: so <requires> is basically like <assert>, and rule is some syntactic sugar to make the asserts conditional on an expr? Or do you want to use the <requires> also for the instruction encoding?
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<zmike>
anarsoul: did
<anarsoul>
zmike: thanks!
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<karolherbst>
robclark: no, it shouldn't change encoding
<karolherbst>
I just want a way to put actual hw constraints into isaspec as well
<karolherbst>
so if some bit is set, it might require an register to be not set
<karolherbst>
stuff like that
<karolherbst>
or it disallows certain other flags
<karolherbst>
we do have some weird things like that
<robclark>
I guess assert does already give you that, but I think it becomes a bit cumbersome for if-this-then-assert-that type things
<karolherbst>
robclark: like.. I still want it to disassemble/assemble, _but_ it should assert at runtime or throw an error saying "well.. it's valid encoding, but invalid to actual run on hw"
<karolherbst>
yeah..
<karolherbst>
normally we don't have to redefine things.. normal vs uniform register is more or less the only thing. Everything else is just validation
<robclark>
maybe assert is badly named, it just prints warning while disassembling..
<karolherbst>
just want to discuss with you how this should look like, so I can already put in the tags, without actually having to change isaspec atm
<karolherbst>
mhhh
<robclark>
the use case was basically to more easily spot bits that show up in blob cmdstream that we don't expect
<karolherbst>
but I also want it to error when used in the compiler
<karolherbst>
yeah...
<robclark>
I suppose that could be added.. main thing I was thinking of at the time was just on decode side
<karolherbst>
maybe assert is good enough as long as it not only works in the disassembler, but also when emiting code
<karolherbst>
robclark: does assert work inside overrides?
<karolherbst>
mhh.. I guess it would
<robclark>
it should.. it is kinda just a special field
<karolherbst>
let me try that actually
<robclark>
(I don't remember off top of my head if we actually use that already, so could be untested)
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<karolherbst>
the only pain point I have with override is, that we have some instructions which have a _long_ list of varriants
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<karolherbst>
but mostly just gpr vs ugpr vs cb...
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<karolherbst>
robclark: but I think it would still be nice to reference existing fields in the hierachy and not having to copy paste low/high
<karolherbst>
but that shouldn't be terrible to add
<robclark>
you should be able to access fields from elsewhere in the hierarchy
<karolherbst>
I know
<karolherbst>
but I meant referencing them in fields/assert declarations
<karolherbst>
like I can't just do <assert name="SRC0">11111111</assert>
<karolherbst>
I have to input low/high
<robclark>
oh, that is what derived fields are for
<robclark>
so you can just combine SRC0_LO and SRC0_HI, etc
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<karolherbst>
sure
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<karolherbst>
but I want them to have a certain value
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