ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<lygstate> :jenatali OK then
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<airlied> ajax: do you think we should be using the xcb_image helper library?
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<airlied> ajax: got the basics for egl shm working, at least the wezterm app displays and resizes
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<FireBurn> Hi, since the outage of gitlab last week my mesa fork gives me CI emails each time I sync it with mesa/mesa
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<daniels> FireBurn: yeah, that's not GitLab-related, that's due to https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16875 which adds a GitHub-only macOS CI run, which currently fails every single time
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<karolherbst> austriancoder: sooo.. let's say a "thing" consists of bits 24..31 + 40..50, but it's "one thing", how would I be able to express that within isaspec?
<austriancoder> karolherbst: maybe like this: https://www.toptal.com/developers/hastebin/qohiqeseko.xml
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<karolherbst> austriancoder: yeah well.. I mean, it's really stupid. It's just a a[gpr + offset] thing, so I could _split_ it, but because I am trying to get as close as possible to nvdisasm I also want to "hide" the reg if it's zero
<karolherbst> but it matters for validation
<X512> dma_buf sync code in wsi_common_drm.c broke Haiku build :(
<karolherbst> some encodings require a zero reg
<karolherbst> or they require the offset to be unsigned (1 bit shorter)
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<karolherbst> austriancoder: well.. my main goal here is to simply share that display override I have
<austriancoder> karolherbst: here is my the bigger part of my xml: https://www.toptal.com/developers/hastebin/giconucafo.xml
<karolherbst> and that's what I'd like to use as a field, but of course that doesn't work because of things in the middle
<austriancoder> karolherbst: you can pass params to a field
<austriancoder> karolherbst: I used it for #instruction-src
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<austriancoder> karolherbst: my isaspec xml might not be perfect :) robclark is the guru
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<tzimmermann> javierm, did you receive the hyperv patch that I sent out this morning?
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<karolherbst> austriancoder: right.. but what if you have a gap
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<javierm> tzimmermann: hi, I did. Sorry, I've been drowned with internal work these past few days
<tzimmermann> javierm, np. i never got them back from the ML. and neither did i receive the replies :/
<tzimmermann> dri-devel didn't like me much recently
<javierm> tzimmermann: ah, I see that mripard and vsyrjala already acked it
<tzimmermann> yeah, i see that on the various online archives, but not in my inbox. anyway, i'm going to land the fix
<javierm> tzimmermann: weird, I've seen delays but my emails and answers do always arrive
<anholt_> one commit here to review for a bit of CI efficiency: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17146
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<robclark> karolherbst: make the non-contiguous field outside of the bitset and pass it as a <param>..
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<karolherbst> robclark: ohh, so I can pass the "fields" as params?
<karolherbst> yeah.. that should work
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<karolherbst> robclark: uhm... any examples on how it would look like?
<karolherbst> ohh.. I think I know
<robclark> karolherbst: I don't have it in front of me but you can look at how "HALF" is passed to the two src reg bitsets in ir3-cat2.xml
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<karolherbst> yeah.. got it worked out, sadly, it's not so nice as I hoped it would be :D
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<karolherbst> robclark: can I also have zero sized fields? like if it's simply a composition of params to make some display stuff shared
<robclark> hmm, try it and see what happens? I guess it isn't an approach that I'd thought of, but probably could be made to work
<karolherbst> yeah.. doesn't work
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<karolherbst> I also have to figure out how to deal with variants of the same instruction
<karolherbst> like I have this weird instruction where either the indirect is set and the immediate is a signed 11 bit value or the indirect is zero and the immediate is an unsigned 10 bit value
<karolherbst> encoding is all the same
<karolherbst> just the reg is 0xff instead of sometihng else
<karolherbst> robclark: I was wondering if we want to add a <rules> thing where you can declare constraints?
<karolherbst> can contain a list of expr which all have to evaluate to true
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<karolherbst> or maybe I just make them different instructions...
<jekstrand> bbrezillon: Can I maybe trade you on some reviews for !15359?
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<alyssa> ok i have a brilliant idea
<alyssa> TGSI shaders in Vulkan
<alyssa> it's a perfect match! ;-D
<karolherbst> noooooooooooooooooooooo
<karolherbst> alyssa: everytime somebody mentions what one can do with TGSI, a cat dies
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<bbrezillon> jekstrand: sure
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<robclark> karolherbst: reg==0xff seems like a thing you could do w/ override expr, right.. you can create named expr's for cases where you want to re-use the same thing in multiple places
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<karolherbst> robclark: yeah.. but it's not just some encoding thing, but the instruction rules might change depending on such things
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<karolherbst> like if the reg is 0xff, you have one bit less for the immediate, because it can't be negative anymore
<robclark> hmm, you can still do that w/ an override, I think.. don't have the code in front of me at just this moment (travelling)
<robclark> but it sounds like it isn't that you have one less bit, just that the high bit must be zero?
<karolherbst> yeah
<karolherbst> essentially
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<robclark> karolherbst: iirc we can't easily use <pattern> in an override, but I suppose you could use <assert> if you want it to complain when high bit is 1 when it shouldn't be
<karolherbst> that would be good enough
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<alyssa> jekstrand: nir_opt_shrink_vectors can shrink an intrinsic producing a vec8 to one producing a vec7
<alyssa> but NIR forbids vec7, causing a validation error if shrink_vectors is used with CL
<alyssa> should we allow all the other vector sizes? or just teach shrink_vectors not to do that?vec6/vec7
<alyssa> On mali, we have a LOAD.i48 instruction, separate from LOAD.i64
<alyssa> It's ovbiously intended for 3x16-bit but could just as well load 6x8-bit
<alyssa> so there's "value" in shrink_vectors from that perspective
<alyssa> ^extending NIR to model other vec sizes
<alyssa> (similarly, vec12 is "interesting")
<jekstrand> alyssa: Wait, how?
<alyssa> Which part how?
<jekstrand> alyssa: How can it produce a vec7?
<jekstrand> There's no vec14 to split in half
<alyssa> shrink_vectors
<alyssa> vec8 8 load_global
<alyssa> but the last component is unused
<alyssa> so it's shrunk to vec7 8 load_global
<jekstrand> Right. That pass probably just needs to be smarter
<alyssa> already started typing out a fix
<alyssa> but again... if only the first 6 components are used of vec8 8 load_global, mali would really prefer vec6 8 load_global
<alyssa> (Maybe.)
<jekstrand> Maybe but I'm skeptical.
<alyssa> understandable
<alyssa> patch I typed makes that test go through validation and I think pass but idk the CL CTS is weird :p
<alyssa> don't have spoons to deal with gitlab rn
<alyssa> meanwhile...
<alyssa> vec16 16 ssa_25 = intrinsic load_global (ssa_24) (access=0, align_mul=32, align_offset=0)
<alyssa> that's not going to work well ^^
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<karolherbst> robclark: can I check for the type inside expr?
<karolherbst> ohh.. maybe I've got a different idea
<karolherbst> ehh no
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<robclark> karolherbst: not entirely sure what you mean by checking for type.. but expr is just C code so in theory it can do whatever C can do ;-)
<alyssa> oh no
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<karolherbst> robclark: mhhh
<karolherbst> robclark: I meant the type I have in XML
<karolherbst> the name actually
<robclark> I don't think that is readily avail in the encode path but might be easier in decode path
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<karolherbst> robclark: here the isaspec example for just one instruction: https://gitlab.freedesktop.org/karolherbst/mesa/-/commit/2e4117038c831f31a2852f6f6caa1bb3290b8ec2
<karolherbst> search for ALD
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<karolherbst> I kind of wished that would be a bit simplier to declare
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<karolherbst> but maybe you have ideas on how to simplify this
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<robclark> karolherbst: one small thing that might help is "offset" and "uoffset" types which display as empty string if value is zero
<gawin> is Gert on IRC?
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<daniels> gawin: he's not I'm afraid - gert.wollny@collabora.com will get to him
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<daniels> he also works central European hours, so he's not around at this time in any case
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<robclark> karolherbst: so, it looks kinda like things like "SRC0" and "SRC1" are always at same bit position, in which case having an extra level of inheritance hierarchy might save some copy-paste.. or Karyon's idea of "mixin" (multiple inheritance kinda) might be a simpler way (if isaspec supported that)
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