ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
<airlied>
dri2 the protocol or dri2 the framework?
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<airlied>
we could probably start to deprecate the protocol, I assume dri3 is nearly everywhere now
<anholt>
I'd feel pretty safe dropping dri2 the protocol at this point.
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<emersion>
would be nice to drop the dri2 layer as well
<airlied>
well I think the layer is pretty much the basis for dri3
<airlied>
at least in egl_dri2 sense
<mareko>
dri2 (not dri3) support in mesa
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<mareko>
glx, egl, and frontend/dri support
<mareko>
whatever is dri2-specific
<mareko>
the dri2 name is overloaded in mesa, and I just mean the X DRI2 support
<mareko>
it's hard to see what is dri2-specific and what is shared right now
<mareko>
removing dri2 would clear that up nicely
<mareko>
the second question is: how much can we break dri_interface.h given glvnd?
<mareko>
a lot of code complexity is due to dri_interface.h being stable
<airlied>
we could in theory collapse dri_interface.h
<airlied>
now that we only have gallium and we have glvnd in place
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<anholt>
airlied: xorg's loader has been a big blocker there, but presumably we could have its usage be one entry into gallium, and the rest of mesa collapse to use gallium directly instead of loader.
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<airlied>
ah yeah I forgot we have to do xorg loader
<airlied>
ajax had some plan to use EGL directly
<airlied>
but not sure where that plan ended up
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<mareko>
I wouldn't like to break old X
<mareko>
I suppose there is a subset of dri_interface.h that we would keep
<airlied>
yeah then dri_interface changes might be limited
<airlied>
or maybe make dri_interface.h just the x_interface.h
<airlied>
and stop using it in mesa itself
<mareko>
yeah
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<daniels>
emersion: please feel free to adopt, I’ve been pulled into some other things recently
<emersion>
ok
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<airlied>
karolherbst: if you have a chance to rerun your llvmpipe rusticl numbers with 19736, I'd be interested in any changes you see
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<mareko>
is it allowed to bind the same drawable to multiple contexts? do we allow it?
<mareko>
the dri frontend has code for it, but I don't see how it could work
<mareko>
I wonder if I can remove it and see if something breaks
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<MrCooper>
mareko: IIRC GLX allows it, maybe not EGL though
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<MrCooper>
mareko: BTW, do you mean multiple contexts as in multiple threads of the same process, or multiple processes?
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<MrCooper>
emersion: do you think your drm revert patch jadahl just followed up on can still land for 6.1?
<emersion>
MrCooper: i don't know, i'm not familiar with the process
<emersion>
it's in drm-misc-next
<emersion>
been there for a while
<MrCooper>
danvet: ^ did that go to the wrong tree maybe?
<javierm>
emersion, MrCooper: was it for a patch that was already in mainline? If that's the case then should had been pushed to drm-misc-fixes
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<MrCooper>
I suspect so, jadahl says 6.1-rc is broken
<javierm>
drm-misc-next is a target for the next merge window, drm-misc-fixes for the current -rc cycle
<danvet>
probably needs a cherry-pick to the right branch then
<MrCooper>
yeah, it's in mainline
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<danvet>
cherry-pick to drm-misc-fixes then
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<MrCooper>
emersion: can you do that?
<emersion>
sorry, no time for this now
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<MrCooper>
don't think any of us had time for this :)
<karolherbst>
airlied: numbers as in performance?
<karolherbst>
yeah, can do
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<jadahl>
MrCooper: emersion: the patches are in no 6.1-rc* yet at least
<MrCooper>
yeah, drm-misc-next is for 6.2 at this point
<MrCooper>
the patches would need to be on drm-misc-fixes to get into 6.1
<karolherbst>
airlied: the biggest thing is thoug, that llvmpipe only reaches like ~70% CPU utilization for whatever reason :)
<karolherbst>
"(
<karolherbst>
:(
<karolherbst>
not sure if something in regards to threading goes wrong
<karolherbst>
with that path it falls down to ~55%
<karolherbst>
*patch
<karolherbst>
780 -> 1200 score :3
<karolherbst>
probably also improves CTS run time (I'll only regression test tho)
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<mareko>
MrCooper: multiple contexts in the same process
<MrCooper>
k, EGL explicitly disallows that
<mareko>
frontend/dri allows binding the same drawable to multiple contexts, but also has drawable->ctx, which happens to be the last context that was bound
<mareko>
so I don't know what to think about it
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* mareko
is flattening the dri_util stuff
<airlied>
karolherbst: the backend doesnt fwnce cs submissions
<airlied>
it syncs all threads after work submit
<karolherbst>
ahhh
<karolherbst>
that explains
<karolherbst>
llvmpipe not using all of CPU might be a good thing actually, but there is still so much free perf
<karolherbst>
a score of 2400 would actually come a bit closer to pocl
<karolherbst>
but let me check how fast pocl really was (I just know it was super fast)
<karolherbst>
90% CPU util, 3800 points. So llvmpipe is around 2000 points if we extrapolate CPU util
<karolherbst>
not bad
<karolherbst>
would be fun to beat pocl tho, but not sure how much work one would have to put into it. Though it could also improve GL performance a little, so might be even worth it
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<airlied>
karolherbst: ill look at fencing compute soon
<karolherbst>
cool
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<MrCooper>
mareko: can't see anything in the GLX 1.4 spec which would forbid it
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<sven>
anyone familiar with drm_connector_oob_hotplug_event?
<sven>
i'm wondering why you get the fwnode at probe time and then pass it to drm_connector_oob_hotplug_event which then gets/puts the drm connector everytime instead of just getting the drm connector at probe time and keeping the reference and passing that to drm_connector_oob_hotplug_event
<sven>
the second way is how e.g. usb role switching does it. the reason i'm asking is because at probe time the drm_connector might still be NULL 'cause the drm driver just hasn't probed yet but I might still want to send HPD there
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<jani>
so no gfx devroom at fosdem?
<devilhorns>
jani, I heard the same thing last week :(
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<danvet>
sven, maybe to untangle module unload lifetime fun?
<danvet>
tbh no idea ...
<danvet>
javierm, do you know hans' nick for sven's question above?
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<danvet>
sven, it does smell a bit like a "works for me" hack, that I agree on
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<danvet>
but I wasn't involved in the discussion at all, so really no clue
<javierm>
danvet, sven: he doesn't use irc that much, sometimes is on libera.chat with the hansg nickname. So better to reach by email I think
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<javierm>
sven: looking at the code I think that agree with you, I don't see a reason to pass a fwnode rather than just a drm_connector
<javierm>
specially since the actual drivers that have a struct drm_connector_funcs .oob_hotplug_event callback expect the latter
<sven>
ok, thanks. i was essentially wondering if there's a specific reason (like disappearing drm_connectors? dunno :)) for getting it every time
<sven>
i'll send a mail once I'm done with the typec side and actually need to look into routing HPD in a sane way
<javierm>
sven: Ok
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<jenatali>
Regarding the label maker, it'd be nice if it was able to add more labels as new changed files are added to a MR
<jenatali>
I get not wanting to override someone who manually set labels, but if the only labels on the MR were already added by the label maker... then adding new ones makes sense
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<eric_engestrom>
jenatali: agreed, but I don't think gitlab's api provides a way to get any information about _who_ added a label
<a1batross>
marex, hello! Thanks for your lt9211 bridge driver. I tried it with dual lvds output... it surely outputs something but it's garbled. I'm waiting response from lontium about that but just in case do you have any ideas? https://cloud.autogramma.ru/s/nyxT96Cf92eZXrC
<a1batross>
also had to fix CHIPID2 from 0xe3 to 0xe4. It seems can float in different revisions (?).
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<DavidHeidelberg[m]>
Is around someone working on Intel mode-settings around? Having real pain with Dell XPS 9310 to be friend with any HD/4K + 4K combination. Always errors, works only occasionally, I can try debug it, but without help it's kinda hard. I already filled bug for TV https://gitlab.freedesktop.org/drm/intel/-/issues/7337 but I'm having similar issues with laptop (usb-c) -> Dell 4K U2723QE (DP) -> EIZO 4K. I never managed run both LCDs at
<DavidHeidelberg[m]>
60hz ever. And 60hz + 30hz works only time to time. And I'm not talking about using 4k+4k+laptop HD display.
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<marex>
a1batross: hey
<marex>
a1batross: I can _try_ and find my notes for that configuration
<marex>
a1batross: hint: I don't have datasheet for the chip, lontium sucks in that aspect
<marex>
a1batross: different chipid may sometimes be due to too high input clock into the bridge, I've seen that, but then the ID was unstable and sometimes random-ish ; do you consistently get 0xe3 in your case ?
<a1batross>
yeah, it's always 0xe3
<marex>
a1batross: maybe with dual-link LVDS, we need to divide DSI clock (assumption?) somewhere
<a1batross>
I asked them for proper datasheet, but sure they won't give it. Initially they wanted to write driver for us if we give them our LCD panel datasheet lol
<marex>
is it really 9211 or some new version ?
<a1batross>
yeah, it's same 9211
<marex>
a1batross: yeah, that's lontium
<marex>
they would give you a wall of random numbers to poke into the registers
<a1batross>
wrong, it's always 0xe4. It's also sits in different i2c address 0x2d than mentioned in public datasheet 0x5a
<marex>
I'll be back in some 20-30ish minutes, then I can look around the notes
<marex>
uh
<marex>
wait ... the chip could be strapped to multiple i2c addresses I think
<a1batross>
maybe. 0x2d is also looks like 0x5a shifted right
<marex>
a1batross: 0x5a >> 1 = 0x2d ... one of them is with the RnW bit (8bit address, 7bit + RnW), the other is 7bit address
<a1batross>
if it's not hard for you searching through your old notes...
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<marex>
a1batross: I will do that, just give me like 30 mins, I have something a bit urgent to deal with first
<marex>
a1batross: btw can you share a photo of the effect you see on the display ?
<marex>
could it be you have the wrong LVDS channel ordering ? odd vs. even pixel thing ?
<a1batross>
I posted a video link above
<marex>
dual-lvds-even-pixels <---- this DT prop
<a1batross>
I checked electrical scheme thrice, it's sure not swapped. Even if I swap them in DT, it still wrong output
<karolherbst>
thogh I got asked to file the bug, which I did last week
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<a1batross>
marex, don't hurry, gonna continue tomorrow, too tired. Thanks for help anyway :)
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<jenatali>
David Heidelberg: Your new alpine container makes the container list just long enough that now I have to scroll to hit play on my Windows CI runs :P
<anholt>
./.gitlab-ci/bin/ci_run_n_monitor.py --target "<job-regex>" --rev `git rev-parse HEAD` can be a bit less painful than the web ui.
<anholt>
not sure why the script requires the --rev argument
<DavidHeidelberg[m]>
jenatali: have you tried 8k LCD? 🤣
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<DavidHeidelberg[m]>
anholt: we could make the rev-parse HEAD default, since I guess most of people using it with the default revision in git
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<DemiMarie>
Any updates on the DMA-Buf coherence situation?
<danvet>
vsyrjala, I thought I fixed up the nouveau fbcon issue ...
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<danvet>
there was a build breakage thing last week on that
* airlied
wonders if vsyrjala has old git
<airlied>
anyways I'll be pushing a -next in an hour or two so should fix it
<danvet>
airlied, just deleting the fixup patch from drm-rerere should sort drm-tip out, since that should break after the merge
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<danvet>
since I should sleep now :-)
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<karolherbst>
airlied: I'm thinking about turning on lower_mul_high for AMD hardware, because I need the 8/16 bit lowering. Do you think it also makes sense for radv?
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<airlied>
karolherbst: the ac emit_umul_high kinda looks like the nir lowering, so it probably would work
<karolherbst>
yeah.. the llvm code is also doing the same thing
<karolherbst>
where would I have to set the flag for radv?
<karolherbst>
because then I can just drop that code
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<airlied>
though aco seems to emit a hw instruction
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<airlied>
the llvm backend might be lowering that pattern
<karolherbst>
heh
<karolherbst>
"interesting"
<airlied>
ah yeah lowering doesn't make sense there then
<airlied>
aco doesn't need it
<airlied>
and it would be worse off
<karolherbst>
mhhh
<karolherbst>
but radv can go the llvm path still, no?
<karolherbst>
or are there different nir_options for both paths already?
<karolherbst>
main reason I want to add it is, that I need it lowered for 8/16 bits as well
<airlied>
just add lowering options for 8/16 maybe
<airlied>
radv uses nir_lower_bit_size for non-32bit umul_high
<karolherbst>
yeah
<karolherbst>
lower_alu also has some code
<airlied>
so it does some 8/16->32, does the op and converts back
<airlied>
and that pass has special umul_high handling
<karolherbst>
okay
<karolherbst>
then I guess I'll be doing that
<karolherbst>
ehhh
<karolherbst>
I thought radeonsi already uses it?
<airlied>
radeonsi just lets llvm deal with it
<airlied>
assuming llvm backend matches the pattern which is quite likely
<karolherbst>
maybe I should fix up nir_to_llvm instead..
<karolherbst>
but it's literally doing what nir is doing :(
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<airlied>
let me check if aco has separate nir options
<airlied>
I think it does
<airlied>
ah no it just has a device->use_llvm flag
<karolherbst>
eh
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