<alyssa>
supposing !20906 were merged first panvk won't care whether lower_blend happens in early or not, currently
<alyssa>
although if we ever did eds3 with dynamic blending, that would require generating blend shaders on the fly for certain blend modes, and it would be cheaper to do that with late blend lowering instead of early lowering (no nir_variables are ever created this way at all!)
<alyssa>
so it's strictly better for panvk long term too
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<alyssa>
Venemo: Thanks for the review on lower_blend, will fix the stuff you mentioned :-)
<pendingchaos>
Lynne: RADV can replace a sampler descriptor load with constant copies
<alyssa>
except the double sign-off, that was deliberate actually
<alyssa>
the panfrost was Collabora billable, the agx was not
<alyssa>
(Ordinarily wouldn't mix those up but there was no way to avoid doing so while preserving bisectability and sanity)
<Venemo>
alyssa: I would have assumed that Collabora's vast fortunes would pay for the 10 minutes it probably took to adjust agx
<alyssa>
Venemo: more to the point, the NIR was not
<Venemo>
not what?
<alyssa>
billable
<Venemo>
:O
<alyssa>
the patch was for Asahi's benefit, panfrost doesn't care right now
<Venemo>
okay, you can keep the double sign off if that helps keep you sane
<alyssa>
heh
<alyssa>
"sane" is not a word usually used in connection to my Mesa exploits :~P
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<Venemo>
c'mon, don't undersell yourself
<Venemo>
didn't you have the highest number of commits?
<alyssa>
dEQP-VK.sanity.*
<alyssa>
NotSupported: 10/10
<Venemo>
ha ha ha
<tzimmermann>
jani, sure, go ahead
<Venemo>
nice one
<alyssa>
and I did until zmike came and decided we should stop writing GL drivers
<alyssa>
and I've been #2 ever since
<Venemo>
who is the first now?
<alyssa>
it's good, takes off the pressure
<alyssa>
zmike: all the pressure is on you, man
<alyssa>
:-p
<Venemo>
wow
<alyssa>
(joking)
<Venemo>
alyssa: regarding the case when the number of components has to be adjusted, I don't even see how it could work in the previous code without triggering validation errors
<alyssa>
IIRC the previous code asserted that it didn't need to be adjusted, and that assertion failed when opt_undef was run first
<alyssa>
but without the assertion it seems to work, maybe
<Venemo>
you can't just change the num components of an ssa def and call it a day
<Venemo>
need to either shrink the vector with nir_extract_bits or enlarge it by appending undefs
<alyssa>
one line up we shrink the vector with nir_trim_vectors
<alyssa>
though er why the heck does the store have a dest
<alyssa>
what is even happening on the old code
<Venemo>
haha
<alyssa>
why the hell are we touching store->dest at all
<alyssa>
that's
<Venemo>
good question
<alyssa>
ok, I think the real answer is that adjusting num_components manually isn't required (since it's already adjusted by nir_trim_vector)
<alyssa>
and the assignment in the old code is a no-op because store->dest logically doesn't exist and physically gets ignored
<Venemo>
right, the store doesn't have a dest so it was just a trap for me to fall into then
<alyssa>
let me split that off
<alyssa>
gotta catch up to zmike's commit count somehow
<alyssa>
i did not become #2 by squashing
<zmike>
make more spaghetti
<Venemo>
zmike: if I ever blog about cpu overhead perf, I'm gonna argue that pasta arrabbiata beats spaghetti any time
<zmike>
brave
<jenatali>
Is there a current chart of top committers somewhere?
<psykose>
yeah you hold the top 10 spots
<alyssa>
all 10 of them
<alyssa>
except for the first 9 which are held by mike
<jenatali>
🥳
<alyssa>
and the last of the 10th which is also held by mike
<psykose>
shucks
<jenatali>
Yeah sounds plausible
<alyssa>
it's because we only count GL driver contributions
<alyssa>
but nobody writes GL drivers anymore because we all write VK drivers
<alyssa>
leaving Mike as the only qualifying Mesa contributor
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* zmike
checks the calendar
<zmike>
does anyone else realize it's not friday
<jenatali>
🤯
<jani>
tzimmermann: thanks!
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<gfxstrand>
alyssa: Yeah, that looks like a pass I could review, given that I rewrote 70% of it a while ago. 😂
<alyssa>
gfxstrand: and I'm deleting that 70% of it! :~P
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<gfxstrand>
alyssa: Awesome!
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<alyssa>
:-D
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<alyssa>
gfxstrand: what's the right Gallium driver to look at as a reference for doing explicit sync?
<alyssa>
Iris? Iris + the Xe patches that havent' merged yet? something else?
<gfxstrand>
alyssa: Probably that or radeonsi
<gfxstrand>
But radeonsi is weird
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<daniels>
radeonsi is 'weird' in the same way that Antarctica is 'cold'
<zmike>
Z I N K
<daniels>
(in the same way that Zink is 'good on tilers')
<gfxstrand>
:P
<gfxstrand>
Actually, Zink might not be a bad thing to look at there
<zmike>
tilers shmilers
<alyssa>
..in the same way that Zink is 'especially good at WSI on tilers'
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<gfxstrand>
alyssa: Are any of us good at WSI?
* alyssa
points to gfxstrand
<gfxstrand>
Not me
<daniels>
define 'good'
<gfxstrand>
alyssa: Ok, dropped you a handful of simple comments on lower_blend. Looks pretty good. I'm mostly just trusting you on the panfrost and AGX bits. Glad to see all that horrible code I wrote go away. :D
<alyssa>
:D
<alyssa>
only thing I like more than deleting my code is deleting other people's code ;~P
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<gfxstrand>
Goodness knows there's plenty of my code to be deleted.
<gfxstrand>
I'm like the anti-ajax
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<daniels>
~/mesa/mesa upstream % wc -l src/vulkan/wsi/*.[ch] | tail -1 && (for i in src/vulkan/wsi/*.[ch]; do git blame $i 2>/dev/null; done) | grep Ekstrand | wc -l
<daniels>
11520 total
<daniels>
3165
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<gfxstrand>
Really? I'm not nearly as to blame for WSI as I once was.
<gfxstrand>
*phew*
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<alyssa>
Lol
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<anholt_>
hmm. Is the "pull present queue" in x11_manage_fifo_queues supposed to be quick? I'm seeing the GPU go idle during it.
<alyssa>
gfxstrand: Weee looks like lower_blend changes hosed Midgard
<alyssa>
Days like this make begrudgingly grateful for CI
<alyssa>
(I tested only on Bifrost)
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<gfxstrand>
alyssa: :(
<gfxstrand>
alyssa: Any idea why yet?
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<alyssa>
Haven't looked
<gfxstrand>
kk
<gfxstrand>
Well, I'm pretty sure it's not my fault. :P
<alyssa>
50/50 coin between "forgetting to update some Midgard-only code path somewhere" and "pre-existing Midgard compiler bug this uncovered"
<alyssa>
my last set of lower_blend changes uncovered a buggy Bifrost opt pass, wee
<alyssa>
I think, I think I work on too many instruction sets
<alyssa>
is 4 not the normal number of ISAs to maintain support for
<alyssa>
what do you guys do? only 3?
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<gfxstrand>
Intel is 2 with different rules at every hardware version.
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<Lynne>
finally got all my code rewritten to use descriptor buffers, then I got a gpu crash running it
<Lynne>
life on the bleeding edge
<zmike>
welcome to hell because there's no way to debug it
<karolherbst>
I think we have 5 ISAs already 🙃
<karolherbst>
nv30/tesla/fermi+kepler1/kepler2/maxwell+pascal/volta+ ohh, I guess 6 it is
<karolherbst>
(that look on gfxstrand's face once I submit support for all of those to NAK I want to see)
<glehmann>
just ignore that old hw exists
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<anarsoul>
glehmann: but how old is old?
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<alyssa>
karolherbst: are those actually different ISAs? not just different encodings?
<karolherbst>
heh.. fair question, depends on what you consider to be a different encoding and what you consider a different ISA
<karolherbst>
they do change stuff in weird ways, so it's not just the encoding being different
<karolherbst>
but things are still close enough that's not really all that different?
<Lynne>
for multi-element descriptor bindings, vkGetDescriptorSetLayoutSizeEXT returns the total size, right?
<zmike>
yeah it's the size of the layout
<alyssa>
karolherbst: yeah, still sounds like one ISA roughly
<alyssa>
when I talk about 4 ISAs I mean 4 radically different architectures spanning 3 NIR backends
<karolherbst>
mhhh
<karolherbst>
guess then we have.. 2.5
<alyssa>
1 vector VLIW, 1 scalar VLIW with completely different VLIW structure and completely different instructions, 1 superscalar with similar instructions, 1 multi-issue from another vendor
<karolherbst>
nv30 is a vec4 ISA, nv50+ is scalar, but volta+ is so different
<alyssa>
yeah that counts as 3 probably
<alyssa>
but isn't nv30 from like
<alyssa>
very old?
<karolherbst>
yes
<karolherbst>
it's not part of codegen
<karolherbst>
:D
<alyssa>
2003, yeah ok
<alyssa>
3 ISAs in 20 years is a nice pace
<karolherbst>
everybody makes mistakes and has a vec4 isa
<alyssa>
Arm goes through 3 ISAs in like 6 years tops
<karolherbst>
yeah...
<karolherbst>
they do change the encoding quite often and make like changes, but usually things are staying more or less the same
<karolherbst>
it's just different
<alyssa>
and it looks like there will be another mali architecture dropping soon (per developer.arm.com resources)
<Lynne>
zmike: there's my problem, I thought vkGetDescriptorSetLayoutBindingOffsetEXT returned per-descriptor sizes
<Lynne>
err, it does, I misread again
<alyssa>
tbd if that's a new ISA (ugh) or just a remarketed tweak on their current gen
<zmike>
Lynne: it's the offset from the start of the set in the buffer
<zmike>
not sure if helpful, but the zink usage is all in one file and may give some ideas