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<Kayden> karolherbst: nir_lower_bit_size is wrecking ufind_msb: http://whitecape.org/paste/lower-bitsize.txt
<Kayden> who even needs the top bits
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* Kayden fixes and adds asserts
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<Kayden> karolherbst: testing https://gitlab.freedesktop.org/kwg/mesa/-/commits/nir-bitsize-fix in CI now, assuming it works I'll open an MR
<Kayden> thanks a lot for catching that
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<jenatali> Oof
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<alyssa> Kayden: R-b, yiks
<alyssa> yikes
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<DemiMarie> Will future versions of Wayland stop relying on DMA fences?
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<bl4ckb0ne> what do you mean
<airlied> mlankhorst, mripard: who's on the fixes watch? I see some drm-misc-fixes I don't have yet
<airlied> I'll hold sending Linus until tomorrow, hopefully someone can dequeue them
<mupuf> daniels: the plan isn't to use netconsole (which is glorified syslog), the plan would be to make a TTY driver over TCP... Once the realtime guys finally land the printk rewrite to make consoles asynchronous
<airlied> mupuf: that's tonights nightmare sorted :-P
<mupuf> DemiMarie: you were proposing a usb-gadgets-based TTY? That's also an option, but I'm afraid some boards wouldn't support being the hosts
<airlied> do arm boards even support usb debug port serial thingo?
<airlied> the thing that needs the special dongle
<mupuf> airlied: ROFL, are you talking about the printk rewrite or... Implementing a TCP version of that?
<airlied> TCP version of tty :)
<mupuf> USB on the go is quite common, but yeah
<mupuf> Well, in the current state of TTY, no effing way this happens
* airlied has one of those ajays devices, but used it once years ago
<airlied> ah ehci debug port, that's the correct name
<mupuf> Never heard of it!
<mupuf> Will check it out
<DemiMarie> airlied mupuf: XHCI also has a debug port
<airlied> someone did try once :-P
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<mupuf> Ha ha, nice airlied :D
<mupuf> I expected a loooot worse... but I'm sure the driver wouldn't work correctly right now for the reasons daniels listed
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<mupuf> xHCI debugging sounds interesting but seems read-only :s
<mupuf> And it would once again require another cable... which is somewhat the point of having TTY over TCP: removing one third of the cables
<mupuf> daniels, is your UART problem long term stability? If so, have you tried resetting the serial adapter between jobs?
<airlied> I don't think it even makes it through a job sometimes
<alyssa> ci is hard let's go shopping
<mupuf> Oh boy... I have some ultra cheap ones I have been using for the steam deck, they start crashing when their FIFO gets full
<mupuf> But I don't ask nearly as much from them as LAVA does
<mupuf> And my fallback plan if this failed would be for my initramfs (b2c) to replace stdin/out/err with a socket to the gateway... But that means no early debug messages
<mupuf> Not that a USB console is much better: I had to add a hack in init.c to wait for /dev/console to appear because device enumeration is do damn slow
<mupuf> So yeah, I have console=ttyUSB0 on some CI machines
<mupuf> I have been dreading sending this patch... It's no different from the wait for root=... so there is at least a precedent
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<kode54> I would test VA-API
<kode54> but nobody on the Xe KMD team wants to touch the <1000 LOC needed to upload firmware I need
<kode54> there must be 3 methods of uploading HuC firmware then
<kode54> because whatever the other cards are using, i915 calls "legacy"
<dolphin> kode54: hardware has indeed changed over generations
<kode54> I know
<kode54> but like
<kode54> the i915 driver refers to the GSC method as if it's the "new way" going forward
<kode54> so apparently that idea was dropped on its ass by Intel?
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<HdkR> What's new becomes old
<kode54> Thanks, Intel
<kode54> guess I'll buy another Intel GPU and hope the story is better
<kode54> the actual story looks like it's supposed to be "buy RDNA2 and nothing newer, or buy Nvidia"
<HdkR> It's not a bad set of choices
<kode54> noooo, I had to be one of the 3 people who bought an Intel Arc card
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<tursulin> mattst88: thanks, glad it is being found useful!
<tursulin> Listing the clients would be like hello world level of complexity.
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<dolphin> <network connectivity level: Finnish train>
<dolphin> kode54: Not sure I fully follow. Loading via GSC is for new hardware
<kode54> then I guess the DG2 has a special way of doing it that's unique to the DG2
<kode54> since the xe kmd devs opted to support tgl and similar but not dg2
<dolphin> yeah, DG2 is in-between
<dolphin> anyway, some parts of VA-API should work without HuC
<kode54> oh
<kode54> in that case, then I'm just waiting on someone at intel-media-driver to upstream something to support xe.ko
<kode54> there was an attempt, but it was specific to tigerlake, and not really more than a proof of concept
<kode54> maybe someone could poke the hornet's nest of an issue on the gitlab and tell all the people who ended up subscribing, that the HuC isn't really needed for most formats
<kode54> at least not on DG2
<dolphin> They should have a rather good table on the github page
<hakzsam> anholt_: would you be able to reply here please ? https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20024#note_1868955
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<dj-death> dolphin: yeah speaking of va-api & Xe
<dj-death> dolphin: I guess there needs to be a plan for explicit synchronization
<dj-death> dolphin: ChromeOS apparently ran into that issue with i915 : https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22937
<dj-death> dolphin: but there is no way to do that workaround on Xe
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<dolphin> dj-death: I thought such a plan has been included from day one, at least it was extensively discussed
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<dolphin> ability to pass a list of BOs that would only be used for implicit sync, VM_BIND would still need to be used to bind those to the page tables
<dj-death> ah right, flagging all imported BOs are external?
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<dolphin> dj-death: for the exact uAPI details you definitely want to check from thellstrom and mlankhorst
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<dolphin> I think my connectivity is bad enough that have to move to reading mail backlog. So talk to you later.
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<karolherbst> Kayden: well.. sadly that's not enough to pass the CTS 🙃 but it does fix a couple of failing tests
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<karolherbst> Kayden: ./build/test_conformance/integer_ops/test_integer_ops integer_ctz causes a similar issue where it asserts on bit_size == 32 in case you wanna fix that as well
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<Kayden> yeah looks like there's no lowering for that at all, adding some
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<LLM_puppy> exploring potential to use integrated GPU compute on arbitrarily large segments of system RAM https://0x0.st/HN7S.txt
<LLM_puppy> hypothesis: Devices with inexpensive integrated GPUs (APUs) might be able to accelerate inference on models greater than 16-24GB in size, without expensive GPU hardware.
<Kayden> karolherbst: added a patch which adds lowering for find_lsb to nir_lower_int64 and then updated the intel patch to use that too. test now passes
<karolherbst> cool
<karolherbst> the remaining fails are like 90% image related and it's clamping being wrong and now I remember why I wasn't bothering
<LLM_puppy> I haven't seen this possibility addressed anywhere so i thought sharing the idea with people who know DRI might be productive. The key question is whether system memory beyond the fixed virtual VRAM defined in BIOS could be accessable to GPU. It seems the answer is 'yes' at least for some APUs.
<Kayden> karolherbst: clamping being wrong?
<karolherbst> border clamping
<karolherbst> CL has insane modes there and requires 100% precision
<Kayden> huh. thought we did all that right
<karolherbst> unorm CL_ADDRESS_CLAMP is what's causing issues
<karolherbst> which is `PIPE_TEX_WRAP_CLAMP_TO_BORDER`
<Kayden> in core/memory.rs:1316 there's a TODO: what's a reasonable default? about translating sampler addressing modes to PIPE_TEX_WRAP... the spec says "The default is CL_ADDRESS_CLAMP." (PIPE_TEX_WRAP_CLAMP_TO_BORDER). you have clamp to edge...
<Kayden> ah
<karolherbst> ahh yeah.. guess I should change the default
<Kayden> odd that we'd have precision issues with border
<karolherbst> but the problem there is, it's a different default
<Kayden> I wouldn't think there'd be any lossy conversions with unorm
<karolherbst> by default I use CL_ADDRESS_CLAMP already, it's just what happens if the driver sees unknown values
<Kayden> ah
<karolherbst> that part should be unreachable anyway
<Kayden> right, makes sense
<karolherbst> I think the clamping is off by one pixel
<karolherbst> intel has some weirdo workarounds in their driver
<Kayden> oh, right, I think I heard about that
<karolherbst> not sure if one of those landed or not
<karolherbst> yeah.. don't think so
<Kayden> have to sleep, unfortunately, let me know if you need any more help with stuff
<karolherbst> gfxstrand has it on a branch somewhere
<Kayden> oh right
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<karolherbst> can't find it :)
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<karolherbst> but I think this is another issue
<karolherbst> anyway, doesn't make the issue go away
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<greyxor> Hello, it's not about devel but i'm not sure where to ask. I have mesa 23.1.0 but rusticl don't work with my RDNA2 Rembrandt APU. Do I need to enable something ?
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<greyxor> Switched to #rusticl
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<daniels> mupuf: yeah it's not a running-time thing, it's that there are about four buffers, and one of them periodically just stops draining, unless and until you powercycle the entire machine
<mupuf> daniels: freaking amazing... and you can't replace that with a USB-based one? Too many of them are broken?
<mupuf> doing the pivot seems tricky
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<daniels> mupuf: not really, no ...
<daniels> the pivot is kinda tricky, but eh, it works, and it would've already been merged if we didn't hit timeouts on dozen
<mupuf> sounds good :)
<mupuf> and thanks for sharing the info
<daniels> np at all - thanks to gallo for all the hard work really, I'm just the hype man
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<gallo[m]> daniels: this work would not advance without your review, so thanks
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<karolherbst> jenatali: there are some people arguing that calls like clFinish, clFlush and clWaitForEvents should flush all queues any event and all its dependencies belong to. I can kinda see this makes sense for clWaitForEvents, but not sure if that's also something we should do for clFinish/clFlush. How are you dealing with that stuff?
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<pq> melissawen, did anyone ever stop to think about what https://patchwork.freedesktop.org/patch/532706/?series=116189&rev=4 does to VKMS performance?
<pq> the whole point of repeating the loops in the conversion functions was to avoid a function call overhead for each pixel
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<pq> mairacanal, did you ever do performance measurements on that ^ ?
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<jenatali> karolherbst: IIRC I do it for finish (since that implicitly waits for events) but not for flush
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<karolherbst> mhhh
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<karolherbst> but a flush without the deps also kinda doesn't make sense, because the events will just end up waiting on the deps anyway
<karolherbst> but yeah...
<karolherbst> dunno
<karolherbst> it's kinda hard to tell if that's something which is actually mandated by the spec or not
<karolherbst> I don't support out of order queues anway, so this is just a little change in the end, but still..
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<alyssa> If this is stupid I can close it but don't like stuff enstaleing
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<melissawen> pq, I don't know if anyone stopped to analyse performance there but you are bringing a good feedback that matches recent findings. mairacanal found a race condition issue on writeback job and it became more likely to happen after this patch you've pointed out. So, this change indeed affected the composition performance, I didn't stop to analyse how much.
<melissawen> I'll take a time next week to check it with her. thanks for reporting
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<MrCooper> when hotplugging a USB-C dock to a machine, is fbcon supposed to show up on a monitor connected to the dock via DP alt mode?
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<mairacanal> pq, melissawen, I can perform some performance measurement next week and bring the results to you
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<mairacanal> I'll keep testing but some preliminary results with the IGT tests:
<mairacanal> igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen - 11.4ms without the patch and 9.7ms with the patch
<mairacanal> igt@kms_cursor_crc@cursor-rapid-movement-512x512 - 26.7ms without the patch and 24.5ms with the patch
<mairacanal> igt@kms_cursor_crc@cursor-alpha-transparent - 20.5ms without the patch and 19.9ms with the patch
<mairacanal> igt@kms_plane@plane-panning-top-left - 11ms without the patch and 11.3ms with the patch
<mairacanal> pq, have you seem some downgrade in performance with the patch?
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<alyssa> Do we have any docs on the difference between pipe_image_view::access and pipe_image_view::shader_access
<alyssa> Oh we do it's in the comment right above the struct
<alyssa> I'm great at reading
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<rodrigovivi> lumag: are you sure about merging the patches through drm-intel-next? it might take a few weeks until that's on drm-next and backmerged to drm-misc.... but also we need some ack from airlied or sima .... another way is to have them all in drm-misc-next
<rodrigovivi> airlied: sima: ack on get https://patchwork.freedesktop.org/series/114473/ through drm-intel-next?
* sima is on a very long w/e back on Monday :-)
<rodrigovivi> jani: ^
<alyssa> mesa/st doesn't set PIPE_BIND_IMAGE_VIEW anywhere does it
<alyssa> *PIPE_BIND_SHADER_IMAGE
<alyssa> how is this not broken on more drivers
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<lumag> rodrigovivi, Hmm. This way, it's up to you then
<lumag> jani, rodrigovivi: I'm fine with whichever way works better for you
<zmike> relying on bind flags is broken
<zmike> everyone knows this
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<alyssa> zmike: surely zink is failing vvl over this
<alyssa> create_bci only sets STORAGE_TEXEL_BUFFER_BIT if BIND_SHADER_IMAGE is set
<alyssa> VUID-VkWriteDescriptorSet-descriptorType-00335
<zmike> nah it's fine
<zmike> see also the listed VVL exceptions in ci
<alyssa> pardon?
<zmike> CI uses VVL
<alyssa> maybe VVL isn't checking this VU then
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<alyssa> oh, that VU is about buffers specifically, I guess
<alyssa> still broken. not sure which VU then
<zmike> I'll save you the time: zink passes the bind internally
<zmike> but nice try finding bugs
<alyssa> yeah I just found that
<alyssa> thanks i hate it
<zmike> 👍
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<alyssa> I don't think I can will myself to move that code to mesa/st.
<zmike> I don't see how you could
<zmike> nothing in GL knows how a buffer will be used on creation
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<jenatali> Woo 8 *_dxil intrinsics deleted so far
<jenatali> Spring cleaning is great
<alyssa> right, but the create new resource with the new bind + blit over the contents dance should be done in mesa/st rather than just passing broken flags
<jenatali> Yeah but it really depends on which flags actually matter for the driver
<alyssa> + possibly a "I don't care give me the pain" CAP that sets BIND_SHADR_IMAGE on everything at creation
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<alyssa> instead of just lying to drivers
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<airlied> rodrigovivi: ack
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<rodrigovivi> thanks
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<alyssa> anybody know if RGB32 buffers are supposed to be valid shader images (or just TBOs)?
<alyssa> I don't see a format qualifier for them so presumably no
<alyssa> yeah I don't think so, thankfully
<zmike> they aren't
<alyssa> :+1:
<alyssa> zmike: so i have a mesa/st patch you're going to hate
<zmike> can't wait
<ccr> "I can feeeel your anger. it gives you focus, makes you stronger."
<alyssa> zmike: ok, tell me why I'm a dum-dum https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23142
<alyssa> prior art - 869e32593a9 ("gm107/ir: fix loading z offset for layered 3d image bindings"), which should probably be reverted and replaced with that MR + a 3 line driver patch
<alyssa> karolherbst: ^
<alyssa> oh wait you're on PTO
<alyssa> forget I pinged
* alyssa unpings
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<karolherbst> alyssa: the issue is tiling
<karolherbst> so if we do 2D operations on a 3D tiled image, we get random garbage
<karolherbst> vulkan allows us to know this upfront as there is a flag for it indicating the application intents to use layers of a 3D image as 2D image views, so we can disable tiling on the z axis, but in GL that doesn't exist
<karolherbst> The nvidia driver apparently detiles or something.. it's all very cursed
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<karolherbst> also.. 3D != 2Darray. Array textures kinda imply you don't want tiling on the z axis, where for 3D ones you kinda do
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<alyssa> oh, hm
<alyssa> personally I would do detile in that case, but shrug
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<daniels> melissawen, mairacanal; thanks for bottoming out the race condition!