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<smaeul>
cheetahpixie: most of them are not GPIOs per se, but pin configuration (mux, pull, drive). so they become references to pin configuration nodes. you could generate the pin config nodes yourself from the FEX, but generally you're expected to reuse the existing ones from the SoC DTSI.
<smaeul>
of the ones that are really GPIOs, some become "regulator-fixed" nodes, others "gpio-backlight" nodes, still others become "interrupts" properties on existing nodes
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<cheetahpixie>
smaeul hmm. are they identical on every board with a particular SoC, then? or can there be differences?
<cheetahpixie>
you're not missing addresses or banks, are you?
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<junari>
for some reason, the memory passes the test with maximum values rows and cols, I'll have to look at it later
<junari>
It's time to build openwrt
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<apritzel>
junari: I guess you will run into problems with TF-A, because that also relies on that cpucfg IP block
<apritzel>
junari: I looked at that, and have some early patch
<apritzel>
junari: for a quick hack, you can just do: $ cp plat/allwinner/sun50i_{r329,h616}/include/sunxi_cpucfg.h
<junari>
apritzel: Thanks, I'll try it
<apritzel>
junari: and can you please put your DRAM code somewhere? I guess jernej would be interested (and could help you)
<apritzel>
junari: also: that was good work to find the RVBAR difference!
<apritzel>
junari: turns out that this is the CPUCFG block that the later SoCs use (R329, and also A133)
<junari>
apritzel: It's all made up of quick and dirty hacks
<junari>
(DRAM corrections)
<apritzel>
I am waiting for an LPDDR3 H313 TV box, so would need to touch and extend this code anyway
<apritzel>
so if you just drop the technical bits, I can take care of the rest
<apritzel>
and seeing what's needed for LPDDR4 *and* LPDDR3 probably leads to better code abstractions
<apritzel>
junari: you did this by reverse engineering the boot0 code?
<junari>
apritzel: okay. I have H616 tv box too, but don't know which ram it use. I worked with it remotely and I just asked my colleagues to connect the uart and short-circuit the FEL button. Maybe it LPDDR3 too. It will come to me soon
<junari>
apritzel: yes, with ghidra
<apritzel>
OK, nice. It seems many newer (and cheaper? H313?) boxes have LPDDR3. The first generation had mostly DDR3
<junari>
As I understand it, these are used chips from mobile phones combined with emmc
<apritzel>
The T95 mini box indeed has some eMMC/LPDDR3 combi chip, from Micron
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<junari>
apritzel: Just copy paste failed. The name of the registers does not quite match
<apritzel>
junari: try to copy the four symbols starting with SUNXI_CPUIDLE_EN_REG from the H616 version of the file
<apritzel>
we would need to figure out if they exist
<junari>
when loading the kernel, there are messages that CPU1-3 is not enabled. Does it also depend on TFA? https://pastebin.com/apCGWrjt
<apritzel>
junari: yes, TF-A provides the PSCI services the kernel uses for SMP
<apritzel>
junari: and exactly the registers to control reset and power of the CPU cores are in this moved region
<apritzel>
junari: do you have more information about that PMIC? A datasheet? Or do you know if it's compatible to some other PMIC? At least the ID seems to be different.
<junari>
apritzel: Yes, I found the datasheet for AXP853T
<junari>
Don't think that it compatible
<apritzel>
junari: ah, right, first Google hit indeed ;-)
<apritzel>
well, seems to contain all the information, so just a matter of diligence, either to compare it to other PMICs, or to sit down and dump the register data into a driver
<junari>
apritzel: I tried to do it, but I don't know if it works or not
<apritzel>
junari: alright, many thanks, some work ahead, but looks doable to clean that up
<apritzel>
junari: do you *need* the AXP support in the SPL, to set up the DRAM power rail? Or is that set to a reasonable default?
<apritzel>
the chip supports DC5SET, so if the board has a resistor from that pin to GND, and the DRAM is actually fed by DCDC5, it should work without that
<apritzel>
(that's the setup we saw on most boards before most H616 boards messed that up)
<junari>
apritzel: don't know, I will try without dc5 set
<junari>
On the SoM I have some voltage test points, but it is not known what they are responsible for
<apritzel>
junari: try to run without I2C and AXP code in the SPL at all
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<junari>
apritzel: Looks working
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<junari>
apritzel: after uncomenting some code that I commented out, spl defines the size incorrectly, but closer. Only 2 GB instead of 1 GB
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<apritzel>
very nice! not having the AXP and I2C code in the SPL is definitely helping
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<jernej>
junari: fyi, in next days I plan to parameterize ODT and bit compensation code, directly with BSP DRAM values, so at least that part you'll be able to remove later
<jernej>
and I'll take a look at rest of your code too over the weekend
<jernej>
so you can write LPDDR4 timing code without of much troubles
<jernej>
(I was able to do it for DDR3 on H616)
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<junari>
jernej: I have met a mention of this, this information will come in handy, thank you
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<apritzel>
smaeul: did you ever play with an A100/A133? I got my A133 tablet into FEL, but it won't let me write to the RVBAR copy, so the 64-bit reset doesn't work
<apritzel>
does anyone know if there needs to be something enabled before accessing the CPU_SUBSYS_CFG block?
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