<smaeul>
this is for sun50iw9p1. it doesn't solve your problem, but it explains the T507 behavior
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<smaeul>
hmm, I don't see any clock gate for CPUX_CFG, so assuming you're in secure SVC, and the register exists, I don't know why would wouldn't be able to write to it
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<apritzel>
smaeul: many thanks for your efforts, and yeah, I am hoping for a simple clock gate as well
<apritzel>
thanks for digging out this T507 vs. H616 confirmation. I will make this a build time decision, though, as we need to pull this off in our early AArch32 code
<apritzel>
I will keep digging in the boot0 disassembly. It's not done early, since the DRAM init is through, and it still doesn't work
<apritzel>
and I am pretty sure I am in secure SVC, but I can double check
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<jernej>
apritzel: I'm working on ODT and bit delay compensation improvements in H616 DRAM code
<jernej>
and while it's easy to update ODT code, I hit a wall for bit delay compensation
<jernej>
first, I'm not sure anymore if it actually sets bit delay
<jernej>
second, it's actually comprised of two different adjustments, which I have no idea what they are about
<jernej>
apritzel: so my question is if I can remove current write level, etc, symbols and just use tpr10 value from DRAM settings as-is
<jernej>
or would that be too much similar original AW code?
<apritzel>
jernej: while I appreciate the idea of having *meaningful* DRAM code, we can only do so much, without further information (and resources to work that out)
<apritzel>
jernej: so if you mean if I would be OK with adding a Kconfig variable called CONFIG_DRAM_TPR10 or the like: sure, if that helps stability and wider applicability of the code
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<apritzel>
smaeul: that secure SVC hint was a good one!
<apritzel>
so I checked that I could read (and write) to SRAM A2
<apritzel>
but in FEL I seem indeed to be not secure: reading SCR hangs, as does writing CNTFRQ
<apritzel>
however an "smc #0" fixes that, but seems to behave differently than the other SoCs