<peterm6881>
hi apritzel yes and no, its a V3LP, which is a low power version of the V3s. MoeIcenowy did a lot of work on the V3s in 2017, but I think officially some is still WIP
<apritzel>
I consider this a supported SoC ;-)
<apritzel>
so is it a development board, or some embedded device using this SoC?
<peterm6881>
its very much a development board but with a core use case using code we've developed
<peterm6881>
lol thats good news the V3s is still considered supported :)
<peterm6881>
the V3LP is a drop in replacement but with low power DRAM
<apritzel>
peterm6881: development board is good, since they have more documentation, including schematics
<apritzel>
do you have it running with some vendor provided firmware and/or kernel?
<peterm6881>
but we are using the approved AXP209 pmic
<apritzel>
peterm6881: and what does "low power DRAM" mean, exactly? is it LPDDR2 or LPDDR3? or just some internal, software transparent power optimisation?
<peterm6881>
apritzel, we're following stable kernel and Buildroot LTS, kernel is currently 6.0.12
<peterm6881>
when new BR LTS is released, we test and also update the kernel at the same time
<peterm6881>
apritzel, let me check
<apritzel>
what U-Boot version do you use? Is it mainline?
<apritzel>
if I see that correctly, the V3s uses the H3/A64 DRAM driver, which does not support LPDDR2 (only DDR2, DDR3, LPDDR3)
<peterm6881>
yes the V3s is being phased out, the V3LP replaces it
<peterm6881>
the only difference is low power DRAM
<peterm6881>
u-boot is 22.01, but this is currently on old LicheePi Zero boards, our new board uses the V3LP, but I dont know what changes we need to make
<peterm6881>
im waiting for a batch of prototypes
<peterm6881>
thats why im hoping to collaborate with someone who understands how we can upstream support for our board
<apritzel>
I don't know how reliable the CNX page is, but it mentions DDR2 DRAM and 1.5V, which does not sound like LPDDR2
<apritzel>
so it's more something like DDR2L (like DDR3L), so using the same protocol, but just a lower voltage
<peterm6881>
no i think they've cut and pasted that, its definitely 1.2V
<apritzel>
which would be good news, since it means it would just run, assuming the DRAM supply/data line voltage is provided correctly
<peterm6881>
the licheePi Zero uses a completely different power management circuit, we are using Allwinner approved AXP209 for the V3LP
<peterm6881>
so apritzel are you saying everything we currently have working on the V3s LicheePi Zero Proof of Concept SHOULD just work on our new V3LP board? u-boot, kernel and Buildroot?
<peterm6881>
My, that WOULD be good news..
<apritzel>
if all you do is to replace the actual SoC: mostly
<peterm6881>
we added eMMC for primary boot
<apritzel>
though you never know what surprises AW have up their sleeves ;-)
<peterm6881>
;) indeed
<peterm6881>
apritzel, can I dm?
<apritzel>
one thing to watch out for would be the power supply for the DRAM: if that's coming from the AXP, and that still supplies 1.8V, that would require a change
<apritzel>
sure
<peterm6881>
apritzel, sorry i made a mistake, not 1.2V, the old V3s was 1.8V DDR2, the new V3LP is 1.5V DDR2
<apritzel>
yeah, I read 1.5V in the CNX article, but LPDDR2 would be 1.2V, so given that information is correct, we should be good
<apritzel>
peterm6881: so if all the components are already supported, it should be fairly straight-forward: you just need to submit devicetree patches to the Linux kernel
<peterm6881>
thanks apritzel
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