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MoeIcenowy>
apritzel: BTW the D1 DRAM controller should be similar to V831/R329
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MoeIcenowy>
(and I had R329 DRAM controller support in my R329 patchset
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MoeIcenowy>
but we should refactor NCAT SPLs to DM
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MoeIcenowy>
BTW R329 may have the most weird clock tree among AW SoCs
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MoeIcenowy>
its DRAM clock is from ... PLL-AUDIO
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smaeul>
in contrast, on H6 I can read back the coefficients, and they match what the driver wrote