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<
jernej >
apritzel: do you know where I can find last attempt for H616 PWM?
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<
jernej >
apritzel: U-Boot 2023.10 doesn't boot on OrangePi 3, DRAM setup is not recognized
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09:50
<
jernej >
hm... it might be something else
09:52
<
jernej >
I mean build environment
10:03
<
jernej >
if you have time, please test
10:13
<
montjoie >
jernej: I start building it
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11:46
<
MoeIcenowy >
jernej: for the HDMI issue of H618, maybe mess with unstandard refresh rates?
11:47
<
jernej >
I don't believe so, since video kernel argument is needed to even try to output something
11:48
<
MoeIcenowy >
oh? the default behavior should be using what EDID says, right?
11:48
<
MoeIcenowy >
BTW I remember Sipeed people say H618 HDMI fails on their 3440x1440@60 monitor
11:48
<
jernej >
it would be certainly interesting to see dmesg output with drm.debug set to 0x1e or something similar
11:48
<
MoeIcenowy >
(Sipeed is also doing something H618, Longan Pi 3H
11:49
<
jernej >
yes, it looks like EDID read fails or don't provide acceptable output
11:49
<
MoeIcenowy >
another board with a dual-M.2 SoM socket (but not compatible with Lichee RV's
11:49
<
MoeIcenowy >
BTW I think EDID timing is sometimes not the very same with standard timing
11:49
<
jernej >
Android doesn't rely on EDID and uses its own timings, so that could explain different behaviour
11:50
<
jernej >
I don't think I have a monitor with 1440p resolution
11:51
<
MoeIcenowy >
Sipeed people say the 1080p LCD monitor at their factory fails too
11:51
<
MoeIcenowy >
jernej: do you have any dump of a failed monitor?
11:51
<
MoeIcenowy >
EDID dump *
11:51
<
jernej >
but when debugging HDMI issues, usual suspect is clock rate
11:51
<
MoeIcenowy >
I think a detailed custom timing could get defined in EDID
11:52
<
MoeIcenowy >
my Dell P2314H's EDID contains a detailed timing block, although it's just standard 148.5MHz timing
11:52
<
jernej >
you mean my 1080p monitor? as I said, it works with zero3, but not with tanix tx6
11:53
<
MoeIcenowy >
this sounds strange
11:53
<
MoeIcenowy >
is HPD detected correctly?
11:54
<
jernej >
I didn't do much of investigation
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11:59
<
MoeIcenowy >
looks quite ordinary for a 1080p
12:00
<
MoeIcenowy >
BTW about HPD, I think on newer Allwinner SoCs they're just some kind of GPIO alternative function
12:00
<
MoeIcenowy >
and easy to be not matched to SoC GPIO voltage level
12:00
<
MoeIcenowy >
I remember the standard GPIO level of HDMI port is 5V
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<
montjoie >
jernej: it works, I re-run the job with network test suite
14:41
<
jernej >
montjoie: Thanks!
14:41
<
jernej >
Main concern here is suspend & sleep, but from what I gathered, ethernet PHYs are not supposed to be powered off, since they have "sleep" bit in one of the registers. I then just updated code for powering on at probe time and powering down at remove time.
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<
jernej >
hopefully, this will go in for v6.9 cycle
14:43
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montjoie >
I have no suspend test suite, and not time to start create one:(
14:44
<
montjoie >
jernej: in my memory opi1+ got the same problem than opi3, did you test it ?
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<
jernej >
no, I don't have the board, but you're right, same fix needed there
14:45
<
jernej >
I believe codekipper can help with testing
14:45
<
montjoie >
I have also the board
14:45
<
jernej >
oh, if you have it, feel free to test :)
14:45
<
montjoie >
if you did the dt patch, I could test it
14:46
<
jernej >
no, I haven't and I have to go, so maybe tomorrow? if you don't do it yourself
14:46
<
montjoie >
same gpio than opi3 ?
14:47
<
montjoie >
for reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
14:48
<
apritzel >
montjoie: yes, the same two GPIOs
14:57
<
apritzel >
montjoie: the changes should be the same as for the OPi 3, you just need to copy&paste them in manually, since the One Plus already enabled the Ethernet node
15:00
<
apritzel >
which probably means we lose Ethernet support for older kernels with the new DT (since they don't know about the two "-supply" properties in the PHY node?) - if that ever really worked on the One Plus
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<
montjoie >
seems to work on opi1+
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