<apritzel>
MoeIcenowy: so are you saying that the DRAM controller IP in the AW SoCs is limited to a fixed configuration, just dependent on the topology (rows/columns/banks)?
<MoeIcenowy>
apritzel: well I say the old ones
<MoeIcenowy>
the H6 one should be flexible
<MoeIcenowy>
yes address map configuration is related to the performance
<MoeIcenowy>
including things like bank/rank interleaving
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<apritzel>
ah, the old ones, that makes sense. Indeed addrmap[] appears in dram_sun50i_h6.c and dram_sun50i_h616.c only
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<jernej>
montjoie: do you have OrangePi One Plus ethernet patch anywhere at hand?
<jernej>
I would like to include it when sending other patches
<montjoie>
it miss the comment about double regulator
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<jernej>
montjoie: thanks, I'll add it and make you as author
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<apritzel>
jernej: montjoie: I think reg_gmac_2v5 should *replace* the reg_gmac_3v3 regulator, shouldn't it? And we would need to lose the phy-supply, which also breaks older kernels?
<apritzel>
which brings up the question of how much of Ethernet did actually work, with the current DT?
<jernej>
It's next on my todo today to check everything
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<jernej>
but I can't really test
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<apritzel>
understood, me neither, but by looking at the two schematics it seems the Ethernet situation is the same: one discrete 2.5V regulator controlled by PD6, and 3.3V for the PHY coming through the PMIC's ALDO2
<jernej>
yeah, I plan to make patch to align DT with OPi3
<jernej>
in regards to ethernet
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<jernej>
hm... ethernet timing is borked in OrangePi One Plus DT
<jernej>
oh, or not
<jernej>
not sure if 200 ps makes difference or not