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<kelp>
Anyone tried to patch ipset within openWRT? I'm having some trouble with it. I seem to be able to make modifications to all user-space applications no problem, but, when it comes to anything within kernelspace, the changes I make dont't seem to be compiled and pushed.
<kelp>
(pushed to device, that is)
<nick[m]1234>
Do you require a public IPv4 address for the build worker infrastructure? Or does it also work via ipv6?
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<zorun>
nick[m]1234: it's fine to put SSH on a different port than 22, so that you can share the same IPv4 address among several workers
<zorun>
it would probably work through IPv6 but I don't know if this has been done yet
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<nick[m]1234>
zorun: thanks. I will do some further investigation for sponsoring build resources to the openwrt project.
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<rsalvaterra>
The big-ass random backport is making the 5.15.44 bump rather "fun"…
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<rsalvaterra>
zx2c4_: Are userspace entropy gathering daemons (like urngd) still relevant, with after your random work?
<zx2c4_>
rsalvaterra: not really, no
<rsalvaterra>
Great! Another package I can drop. ;)
<zx2c4_>
I'd rather the energy that goes into that stuff be redirected toward improving kernel rng
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<dwmw2_gone>
We shouldn't need Legacy IP, surely? Everything should work over IPv6?
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<olmari>
dwmw2_gone: tell that to your average ISP
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<dwmw2_gone>
this was just for the build system though, wasn't it?
<dwmw2_gone>
Most of that resides in the 21st century.
<dwmw2_gone>
Hell, I was in the car earlier today and tethered via my phone and I *only* had IPv6; no Legacy IP at all except via NAT64
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<champtar>
ynezz: thanks for the merge!
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<f00b4r0>
well wow. The qca9561 bias fix patch was backported all the way back to 4.9 :)
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<mrnuke>
I've been scratching my head about this for a while. I have a switch with two SFP ports. each port has a diferent GPIO connected to its SDA line, but both SFP ports share the same SCL line. Is there a way to model this in devicetree?
<svanheule>
mrnuke: I'm afraid not. AFAICT there is no way you can currently model a shared SCL line for multiple I2C busses (as some sort of mux)
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<mrnuke>
svanheule: I was afraid that might be the case. I wonder if some enginerd at Engenius decided to get smart, or if they accidentaly messed up the board layout and had to improvise
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<robimarko>
svanheule: Wasnt Birger working on exactly that?
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<svanheule>
mrnuke: I think it's "someone at Realtek," because about half the devices do this real smart trick
<svanheule>
robimarko: not that I'm aware of. I've had a look at it a while back, but didn't finish that
<robimarko>
svanheule: These RTK-s look like they are broken in every possible way
<mrnuke>
robimarko: Thanks for your explanation yesterday. Makes a lot more sense now
<mrnuke>
For some reason I thought a port requires an sfp handle
<robimarko>
Only if you want a proper SFP integration, meaning that the SFP gets attached to netdev
<svanheule>
robimarko: they really tried to nickle-and-dime every aspect of these devices
<robimarko>
And then it can be reconfigured based on the plugged SFP, and you can read it using ethtool
<svanheule>
robimarko: these devices usually have GPIO-s plenty with an RTL8231, so I don't even see the point of doing it in most of the cases
<robimarko>
svanheule: Thats is what gets me triggered usually
<robimarko>
When they do stupid things for no reason
<mrnuke>
I love how they used a GPIO based I2C bus, where the GPIO is an external chip configurable over a serial protocol
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<svanheule>
mrnuke: it gets better: the RTL8231 can even be configured to use I2C
<svanheule>
but you really need a separate I2C bus per SFP-cage, because the 0x50/0x51 addresses are fixed
<robimarko>
svanheule: The thing is that they could have easily used I2C muxing
<robimarko>
But that costs money
<mrnuke>
and RTL8231 don't?
<robimarko>
Well, they are here anyway
<mrnuke>
My device has two RTL8231. I couldn't quite figure out what the second one is for
<svanheule>
mrnuke: typically one is configured as a 36-bit (37?) shift register to driver ethernet port LEDs
<mrnuke>
but the first one -- has about 2/3 of its GPIOs unused. COuld have had that extra SCL somewhere
<mrnuke>
svanheule: I think it is configured as a shart register, if I buzzed out the pins corrctly
<svanheule>
mrnuke: why would you do it that way? If you're willing to settle for one functional SFP, you can just specify one i2c-gpio bus with the shared SCL and its specific SDA lines
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<mrnuke>
svanheule: can you show me what you mean?
<robimarko>
svanheule: Is qsgmii correct PHY mode on DGS-1210-28?
<robimarko>
To me it makes no sense
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<robimarko>
Unless its one PHY with 4 ports using QSGMII
<svanheule>
robimarko: rtl8382 doesn't have any internal PHY, IIRC, so all (8-port) phy-s connect via QSGMII
<svanheule>
wait, that wouldn't have enough bandwidth for 8×GbE, would it?
<robimarko>
Nope
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<robimarko>
Cause QSGMII will give you 4x SGMII links
<robimarko>
And these are old school 1G ones
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<mrnuke>
Speaking of (q)sgmii, How can we tell if an SFP slot should be declared as phy-mode="sgmii" or "1000base-x"? I would think it can't be SGMII because an SFP doesn't have the differential clock lines required of sgmii
<robimarko>
Though, If I attach an SFP bus it all goes to hell
<mrnuke>
Oooh! Datasheets! Nice!!!
<robimarko>
As PHYLINK is reconfiguring it into 1000Base-X
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<robimarko>
And then both copper and fiber dont work
<svanheule>
mrnuke: don't get your hopes up, that's all we have and it's basically an extended list of features
<mrnuke>
svanheule: it's better than "Big black chip thingie with heatsing glued to it"
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<mrnuke>
So how does an SP work in SGMII? There would be one data pair, and one clock pair. So you could get either transmit, or receive, but not both, right?
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<robimarko>
mrnuke: You have TX+/- pair and RX+/- pair
<mrnuke>
robimarko: that's 1000base-[something] then. Unless you can do SGMII without the clock pairs?
<robimarko>
AFAIK, they use clock recovery instead
<Lechu>
Hi, could someone from (preferably) core devs take a look at my RFC regarding link state reporting of ath79 internal switch? https://github.com/openwrt/openwrt/pull/9971