ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<amarioguy>
marcan: btw quick m1n1 architecture question real quick, what exactly determines whether a guest exception (like MSR traps) is handled by the C side or the python side?
<sven>
probably everything that’s triggered very often is handled in the C code
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<marcan>
amarioguy: whether it needs to be fast or not :p
<marcan>
there are actually 3 tiers for sysregs: fast (does not take the BHL), normal (takes the BHL), and python
<marcan>
every tier tries to handle it in sequence, if nothing does you get dumped into an exception shell (though for sysregs I think the default handler is passthrough for everything)
<marcan>
amarioguy: also yeah, I think the SMC trap bit went away, but I don't know if it moved somewhere else or it's now always enabled or what
<marcan>
if I had to guess it'd move to HACR?
<marcan>
ah but ^^ this applies to M2 and newer, T600x should still have the old trap bit
<maz>
with NV, HCR_EL2.TSMC should apply.
<maz>
s/TSMC/TSC/
<marcan>
ah, that explains why it went away
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<amarioguy>
alright got it, thanks for explaining!
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<sid-linux>
Question regarding Asahi Linux ALARM initrd.
<sid-linux>
Where do all the `msg` issued in the initrd phase go? How can I access them?