ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<chadmed>
marcan: were you planning to adopt speakersafetyd? ive merged your changes back into my repo and we can yeet the local version of the alsa crate now
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<sid-linux>
Hi ! I am looking at the apple dtsi, specifically t8112.dtsi in the asahi source
<sid-linux>
we have the aic interrupt controller
<sid-linux>
what is the parent interrupt controller for the aic controller ? is it the gic ?
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<sid-linux>
Ultimately every interrupt controller feeds into the GIC correct?
<chadmed>
did my messages not send
<chadmed>
ah theyre not in the logs
<chadmed>
aiui these socs do not implement gic
<sid-linux>
chadmed: thanks ! In m1n1 source code we have various exception handlers for IRQs, FIQs. How is the cpu core triggering these exception handlers then? FIQ would probably be triggered by timer interrupts but then what about IRQs
<chadmed>
AIC routes them to the application cores
<sid-linux>
So instead of GICv2/GICv3/GICv4 etc. we have AIC2 directly connected to the interrupt pins then?
<sid-linux>
cpu interrupt pins
<chadmed>
yeah AIC sits where GIC does normally aiui
<chadmed>
i _think_ that timer intterupt FIQ thing only applies to the original AIC too but dont quote me on that
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<sid-linux>
if you look at /proc/interrupts there are numbers in the first column e.g. `33:` `34:` etc.
<sid-linux>
basically I'm trying to understand what namespace these numbers belong to. I read somewhere that aarch64 cpus have a certain number of PPIs (private peripheral interrups) and SPIs (Shared peripheral interrupts)
<sid-linux>
Now I'm trying to understand that this is something that GIC offers or is this a property of the CPU (that may or may not have GIC as apple doesn't seem to have)
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<sid-linux>
figured it out -- the `33:` etc. numbers in /proc/interrupts corresponds to the logical irq number in linux
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<sven>
yeah, and just to confirm: the root interrupt controller is the AIC on apple machines
<sven>
they also have a (somewhat broken) virtual GIC but that’s only relevant for VMs
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<sid-linux>
thanks sven ! regarding the broken virtual GIC -- yes I was looking at the kernel source code. all accesses to the interrupt ack register ICH_IAR1_EL1 are trapped
<sid-linux>
(if accessed in the VM)
<sid-linux>
so kvm would have to emulate that
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