ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<amarioguy>
hmm how is u-boot able to do 16bit/8bit writes to some PCI BAR registers on Apple chips? trying those same writes myself results in an SError with L2C_ERR_INF=0x2
<amarioguy>
indicating i think that the bus only allows 32 bit writes per the asahi docs
<amarioguy>
at least to those registers
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<amarioguy>
prime example being writing ASMT_REG_ADDR during fw upload
<sven>
pci isn’t *that* broken, iirc 8/16bit wide access has always worked there
<sven>
no idea why you get an serror though
<amarioguy>
hmm odd, i've been combing u-boot traces/source to see what you're doing that isn't working on my end, not sure why the 16-bit write to the same register isn't being accepted in my case
<sven>
but I guess 32bit wide access works for you? I.e. it’s not just a broken pci init sequence?
<amarioguy>
i'm going to try that actually
<amarioguy>
i adapted the u-boot asmedia xhci code for what i'm doing, 16 bit write and all but who knows if i missed smth
<jannau>
is pcie clock or power-gated?
<sven>
yeah, this very much sounds like something‘s wrong with the pci controller itself to me
<amarioguy>
i wouldn't be surprised honestly
<amarioguy>
jannau: doesn't seem like it? at least edk2 can enumerate devices on the bus and ECAM space can be written to, but i'm not 100% sure if this means that it isn't power/clock gated in some way
<amarioguy>
i've not had problems with ECAM space so far fwiw, mainly just writing to/reading from BAR registers
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<sven>
can you read any bar at all without an serror?
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<amarioguy>
nope
<amarioguy>
looks like smth is wrong with PCI controller startup after all
<amarioguy>
not even a 32 bit read works lol
<amarioguy>
so yea back to figuring out how to get this working properly :/
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