ChanServ changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | Non-development talk: #asahi | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<jannau>
chadmed_: the dcp overlay one produced unexpected tests results in igt-gpu-tools which I've not investigated further (you can't easily check yourself since driver misses things)
<jannau>
I'll write more into the PR later today
<jannau>
I haven't looked at the hwmon fan PR yet
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<chadmed_>
jannau: all good, thought there might be something :)
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<sven>
nickchan: nice work on the aic support for pre-M1 SoCs. looks mostly good to me now :)
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<nickchan>
sven: by the way the devicetree patches might come a bit later since there's some additional troubles with the uart
<nickchan>
besides the SError issue which already have a fix
<nickchan>
on A7-A9 uart rx is partially broken, it only happens in chunks of 16 bytes
<sven>
sounds good to me
<nickchan>
it is not that important for the serial0 debug console but it would be problematic for the other uarts, so I would like to fix that first
<sven>
im happy someone actually makes this all work on older socs
<sven>
I haven’t worked on the UART at all so no idea what’s going on there :/
<nickchan>
for the devicetree part it will exclude some SKUs due to testing issues:
<nickchan>
- All T2 iBridges
<nickchan>
- the HomePod
<sven>
sure, we can always add them later once they’ve been tested
<jannau>
re cpuidle: I've excluded the pre-m1 platforms with `of_machine_is_compatible("apple,t8015") ...` in apple_cpuidle_init and will push that soon to github
<nickchan>
now because of the ridiclous amount of SKUs here - not every other SKU is actually tested, but every SoC/device type combination is tested
<nickchan>
eg: A8 iPhone, A9X iPad Pro, A10 iPad
<nickchan>
But for example the cellular A9X iPad Pro is not tested while the wifi one is
<chadmed>
that shouldnt really matter if the lte modem is just a platform device type thingy hanging off an iommu
<nickchan>
Apple TV are also tested though Apple TV 4K is most annoying to actually use Linux with
<nickchan>
since the USB exploit can only be performed with the USB pins in the ethernet port
<nickchan>
though we did manage to test it on that
<chadmed>
huh... did you test dcp on the atv 4k at all?
<chadmed>
asking for a friend
<nickchan>
Dcp doesn't exist until A14
<chadmed>
oh yeah
<nickchan>
the display on these devices are more similar to the z2 touchscreen stuff for the touchbar mac
<nickchan>
but that also does not apply to Apple TV
<chadmed>
atv's features are more like dcp-lite i suppose
<nickchan>
cpufreq (at least on A10) and wdt is exactly the same
<nickchan>
a10(x) is a mess of cpufreq
<nickchan>
there's the normal a10 that goes up to 2.34 GHz
<nickchan>
a10x goes up to 2.4 GHz
<nickchan>
and then the iPod touch 7 that can only go up to 1.6 GHz
<nickchan>
though other SoCs im dealing with like A7 are also like that
<nickchan>
haven't have luck locating the performance controller from the adt though
<nickchan>
a10(x) is directly from corellium
<nickchan>
also has the lower p-states frequencies artifically adjusted
<nickchan>
since the lower p-states are the zephyr core
<nickchan>
and the higher p-states are the hurricane cores
<nickchan>
userspace absolutely does not expect a lower frequency to have more performance than a higher frequency
<nickchan>
due to the core type
<nickchan>
so it has been adjusted so that performance scales roughly linearly
<nickchan>
dividing all e-core frequencies by 2.65 seems to do the trick
<chadmed>
nickchan: this is a dealt with problem, use capacity-dmips-mhz
<chadmed>
normalise to 1024 on the pcores
<chadmed>
and if you can use opp-microwatt but that might be hard if you cant measure power
<chadmed>
schedutil does the rest for you mostly-accurately
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<nickchan>
there isn't a pcore and ecore to software
<nickchan>
it is cores that suddenly changes performance when crossing a certain p-state
<nickchan>
(and ability to execute aarch32)
<chadmed>
do they have some thing in front of the cores that migrates their state between clusters at the transition? lmfao
<chadmed>
thats insane
<nickchan>
and due to this one of the patches that I have is a gross patch that pretend a10 does not support 32 bit el0
<nickchan>
it doesn't seem like it's a good patch but I do not have other sensible solutions
<nickchan>
chadmed: I think those parts are just fused
<nickchan>
A10 "Fusion"
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<jannau>
nickchan: pushed those thanges to asahi-wip / asahi-6.10.7-2
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<nickchan>
jannau: you missed quite a lot of compatibles
<nickchan>
at the very least apple,s5l8960x also needed to be excluded
<nickchan>
now the devicetree stuff is very much downstream and things could change but we currently do not make the skus based on the AX-series SoC to have the base A-series SoC compatible
<nickchan>
so that's apple,t7001, apple,s8001, apple,t8011
<nickchan>
and then there's TSMC A9 which is apple,s8003
<nickchan>
and finally apple,t8012 would be for the T2
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<nickchan>
given that the t6001 machines were not given the t6000 compatibles
<nickchan>
all skus will only been given its own soc-specific compatible and not some compatible of a similar soc as far as soc-based compatibles go
<nickchan>
for difference between s8000 and s8003: midr is different and the chicken bits to be applied is also different
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<nickchan>
now because this is a downstream driver
<nickchan>
jannau: you can also do a runtime check by checking whether bit 0 of s3_5_c15_c5_0 is RES0
<nickchan>
this is the disable wfi retention bits
<nickchan>
on the asi mac this can be set
<nickchan>
on a7-a11 it is res0
<nickchan>
remember to clear the bit after testing! otherwise you will get the a7-a11 behavior even on m1
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<nickchan>
im actually not super sure need to check
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<nickchan>
okay it's res0 at least on the iPhone X
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<nickchan>
for tracing on a7-a11 currently im thinking of hijacking a core and use the debug registers to debug the other cores
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<nicolas17>
chadmed: "Unlike most implementations of big.LITTLE, such as the Snapdragon 820 or Exynos 8890, only one core type can be active at a time, either the high-performance or low-power cores, but not both. Thus, the A10 Fusion appears to software and benchmarks as a dual core chip."
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<nicolas17>
"The A11 uses a new second-generation performance controller, which permits the A11 to use all six cores simultaneously, unlike its predecessor the A10."
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