#asahi-gpu on 2023-07-31 — irc logs at oftc.irclog.whitequark.org

2022-12-21 00:46 ChanServ changed the topic of #asahi-gpu to: Asahi Linux GPU development (no user support, NO binary reversing) | Keep things on topic | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-gpu

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21:52 <alyssa> dougall: oof. the write-after-write hazard woes are not behind us like I thought :(

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21:55 <alyssa> https://rosenzweig.io/broken.txt

21:55 <alyssa> this is flaking

21:56 <alyssa> (if the ldcf registers are non-overlapping and the moves are removed, it works..)

22:11 <alyssa> some blob output with lots of ldcf instructions https://paste.centos.org/view/84334941

22:12 <alyssa> I notice that bit 46 is set unpredictably, no idea what it means

22:13 <alyssa> (bit 52 is set only on the first -- that's the helper invocation discard bit, much less interesting)

22:15 <alyssa> I have no idea how to coax the blob into doing more interesting things with ldcf to figure out how it deals with the hazard

22:16 <alyssa> ldcf definitely handles WaW hazards with itself

22:16 <alyssa> but what about ldcf about with ALU?

22:18 <alyssa> ..I don't see any ALU writes after ldcf writes to the third register...

22:18 <alyssa> coincidence, I hope

22:20 <alyssa> ok, coincidence yeah

22:20 <alyssa> it will do ldcf-read with alu-write with alu

22:20 <alyssa> with .discards

22:28 <alyssa> i wonder if there's some sort of instruction grouping mechanism we've somehow missed.

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