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<lina>
Mary: Those "out of slots" messages mean you're out of global GPU resources... it's supposed to just block until they free up then, but those codepaths haven't been tested much so I wouldn't be surprised if things go wrong...
<lina>
Maybe reduce the parallelism?
<lina>
(This whole thing is going to be redesigned in the driver so I don't really want to try to fix it if it's broken right now ^^;;)
<lina>
Actually no, I think what happened there is the GPU firmware crashed/froze
<lina>
This is a known issue when you get faults, there's a chance it might happen and I don't know why yet
<lina>
Running out of slots is normal then because all GPU jobs gets stuck...
<lina>
If you get "Job timed out on the DRM scheduler" then things are going to break
<alyssa>
note to self: enabling layered rendering entails
<alyssa>
- setting "set whn reloading z or s 2"?
<alyssa>
- setting fb layers
<alyssa>
- additional varyings as known
<lina>
alyssa: I'll review your MR later (sorry, got caught up in apartment/move stuff last night... still setting up wiring and stuff ^^;;)
<alyssa>
all good
<lina>
Does layered rendering work on the Linux driver? I think that was never really tested
<alyssa>
Unclear
<alyssa>
Well
<alyssa>
No, but I don't know if it's my bug or yours or both
<lina>
^^;;
<lina>
Could easily be mine
<lina>
That was implemented blind and I wouldn't be surprised if I missed some *layers somewhere...
<alyssa>
ah..
<alyssa>
unfortunately I don't have a good test case yet
<lina>
BTW today I wanted to look at something simple as a bit of a walkthrough some reversing stuff, think YUV textures are okay?
<lina>
I figured it's not too complicated to explain ^^
<lina>
Just going to look at the descriptors
<alyssa>
sure
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<alyssa>
lina: nice!
<alyssa>
and I've got you a minimal test case for layered rendering
<alyssa>
branch is agx/layered, information on how to test in the commit message
<alyssa>
The way this is /supposed/ to work is that there is a special 32-bit varying written by the vertex shader contained the layer and viewport ID packed together
<alyssa>
and also we write the layer as a regular flat varying so it's accessible in the frag shader
<alyssa>
and that branch forces eMRT always, so just needs to handle doing image array writes from the frag shader with the layer given by that layer varying
<alyssa>
however... I think the hardware tiler bit isn't working properly
<alyssa>
which could mean either shader bug (possible but I've read the asm and it looks fine..)
<alyssa>
or kernel bug with the layered bits
<alyssa>
forcing pass type to TRANSLUCENT changes the failure slightly which is a smoking gun for that
<alyssa>
good luck :3
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<alyssa>
lina: ^^ (stride / 16) - 1
<alyssa>
my guess is that's the stride of the second plane, with the appropriate shifting/biasing done to pack
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<lina>
Yeah, that was my guess too ^^
<alyssa>
I hope you can figure out the layered rendering mystery because I'm p stuck :(
<lina>
It's probably a kernel snafu...
<alyssa>
could also be a mesa snafu
<alyssa>
por que no los 2
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<alyssa>
lina: OK, it's almost definitely kernel
<alyssa>
I've added a patch which disables hw layered rendering and uses only the sw emulation path, and that passes the test
<alyssa>
so I just need help getting it to pass with that commit reverted ^_^
<alyssa>
also after that, passing ./amd_vertex_shader_layer-layered-depth-texture-render which will be more kernel stuff (or ZLS control bits)
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