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<marcan>
rosefromthedead: you probably need an isb, those counters aren't synchronized
<marcan>
also there could be an offset on the virtual counter for some reason
<marcan>
also I assume you're not running this on the hypervisor, right? that *will* screw with timekeeping on purpose by default
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<rosefromthedead>
marcan: not on purpose, just a normal asahi install
<rosefromthedead>
will try with an extra isb, i already have one before the read but ig it would make sense to need ones either side?
<marcan>
yeah, otherwise it could in principle speculate through the actual work submission to the GPU and all that
<marcan>
I've seen these damn things speculate through an IRQ enough to break some code missing a barrier, it's nuts
<rosefromthedead>
blimey
<marcan>
found a years-old Linux core workqueue code bug
<marcan>
no other ARM64 CPU managed to hit it apparently
<sven>
same thing inside the dwc3 driver
<rosefromthedead>
hmm, still getting some negative durations, but i think less now?
<rosefromthedead>
lol
<rosefromthedead>
i'll check for an offset
<sven>
there was this one subtle role switch bug where they read the new role outside of the mutex or something
<sven>
triggering that requires both a very fast role switch and a very fast cpu that likes to speculate a lot
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<marcan>
rosefromthedead: what machine?
<rosefromthedead>
m1 mini
<marcan>
no ECV then, so no second offset
<marcan>
rosefromthedead: I wonder if there's just a slight offset with the GPU timer for some reason. I don't really know what the internal architecture is like. I know there's one master AIC timer which I think everything derives from, but not how all the downstream timers are synced from that
<marcan>
how negative are you getting?
<rosefromthedead>
only on startup of tinywl for some reason, -3150us, -94us, and everything positive from there
<rosefromthedead>
it's also possible that my code is just mixing up values from different batches or something
<rosefromthedead>
not sure how conscious i was when i wrote it
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<alyssa>
lina: I see the uapi lets you submit multiple commands in one ioctl .. is this tested?
<alyssa>
Mesa doesn't currently use it so IDK if that kernel path was ever exercised
<alyssa>
I have a branch using it but am getting a race condition, second command isn't waiting for the first one to complete
<alyssa>
unsure if this is my bug or yours
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<alyssa>
(When the two commands are in separate ioctls with syncing it works)
<alyssa>
specifically, I want to submit both a compute job and a render job in the same ioctl, where the render job depends on the compute
<alyssa>
(this requires a big refactor of how we submit batches in Mesa, but it seems far less ugly than the alternatives since it avoids messing with delicate batch tracking logic. and its probably faster.)
<alyssa>
Is this.. supposed to work though?
<alyssa>
specifically, I don't understnad the drm_asahi_cmd barriers
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<alyssa>
I want a barrier between my second command and my first. Can I express that?
<alyssa>
If not under the current uapi, can that be added? Working around this in Mesa would be annoying because it splits up the syncobjs and such across multiple ioctls when ideally it would be just one
<alyssa>
I've hacked around it in Mesa for now (submitting two ioctls back to back, putting the in syncs on the first and the out syncs on the second) but I shouldn't have to, I don't think
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<alyssa>
if this is a kernel bug (rather than something that's just not supported yet) I can push a mesa branch to test against
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<lina>
alyssa: It should work. You need to specify the barriers correctly for it to work, yes.
<cyka_delik>
test
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<lina>
alyssa: The first (compute) command needs to specify the barriers as {0, 0} to wait for any previous submission (implicitly, we always do this in GL, no need for sync objects), and the second (render) command needs to specify the barriers as {NONE, 1} to wait for the compute command to complete
<lina>
If you were passing 0,0 for both then that wouldn't work, that would tell the render command to wait for any render/compute commands *prior* to the submission you're making right now
<lina>
So not the compute command that precedes it in the same submission
<lina>
Also even with two separate ioctls you shouldn't need syncobjs as long as you still have the {0, 0} barrier (which maps to BARRIER_RENDER | BARRIER_COMPUTE in the existing code)
<alyssa>
"Right now, the Gallium driver only issues single-command submissions and always uses [C0, R0] barriers to fully serialize everything. This might be improved in the future, but the main use case for all this is Vulkan queues."
<lina>
wwwwwwwwwwww
<alyssa>
I've got a use case :>
<lina>
Assuming we don't find a magic mesh shader thing to make it work ^^
<lina>
I should trace that...
<alyssa>
make which work?
<alyssa>
interleaved compute/vertex?
<alyssa>
it would be really nice if they added it
<lina>
Yeah ^^
<alyssa>
Mali can do it, it's not fundamentally hard
<alyssa>
or particularly magic
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<alyssa>
you just.. merge the VDM and CDM into one big queue. that's it.
<alyssa>
PVR can't do it though, I asked
<lina>
I should sleep but I can try looking at this later ^^
<alyssa>
take your time, I have work tomorrow and will have to put this branch down :V
<lina>
Also can you look at the shadowing MR? It's kind of a nasty bug/thing but the fix is easy, I want to get it fixed ^^
<alyssa>
yeah, tomorrow
<lina>
OK ^^
<alyssa>
this isn't a work day for me it's a guilty agx pleasure day, no review :>
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<ella-0>
alyssa: the agxv queue stuff uses multiple commands per ioctl
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<alyssa>
:+1:
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