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<ishitatsuyuki>
good question, and apparently a 0 propertyFlags is explicitly allowed
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<linkmauve>
“09:35:55 emersion> but dumb BOs are not for clients…”, what would be the recommended way for clients to do software rendering into buffers they expect to be used as dmabufs? I’m thinking about software image/video decoding to maximise the chances it gets promoted to a plane.
<emersion>
someone, compositor or client, needs to upload to the GPU
<emersion>
the compositor can upload to a scanout capable buffer if it wants to
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<linkmauve>
emersion, does that mean it’s useless to try to optimise software decoding with a dumb buffer allocated from the kms device, and instead we should use GL or so to upload it anyway?
<emersion>
hm, so, maybe you'd want to write directly to the dumb buffer to avoid copies?
<linkmauve>
That’s my reasoning yes.
<emersion>
although shadow buffers are preferred most of the time
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<linkmauve>
Let’s say I’m a very simple video application, using ffmpeg or similar library in software-only mode, and I want to get the best possible path towards the screen.
<linkmauve>
I do not use GL yet.
<linkmauve>
I would expect dumb buffers to provide said best possible path, at least scanout.
<linkmauve>
It won’t be tiled or anything, but for scanout that’s sensible on most hardware.
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<mripard>
linkmauve: another related topic is that dumb buffers (on most ARM platforms at least) is mapped non-cacheable, so software access will be painfully slow
<linkmauve>
Hmm, so it’d be better to decode into a normally-allocated (e.g. malloc()) buffer, and then use wl_shm to let the compositor do what it thinks is best with the buffer?
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<linkmauve>
That way memory access won’t be too slow on decoding.
<MrCooper>
certainly if there's a non-0 chance of CPU reads from the destination buffer
<dottedmag>
There's a capability that tells that dumb buffer is slow on reads/non-sequential writes. I'm not sure how reliable this cap is.
<MrCooper>
DRM_CAP_DUMB_PREFER_SHADOW
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<doras>
emersion: do you happen to know if any DRM display driver currently implements a slew rate for variable refresh rate in kernel or firmware?
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<emersion>
amdgpu has LFC
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<emersion>
intel hw supports some stuff but not sure it's enabled on Linux
<doras>
emersion: do you have any pointers regarding Intel's support where I can learn more about it?
<emersion>
only heard about it in this channel iirc
<emersion>
maybe ask in the intel channel
<doras>
emersion, zamundaaa: have you tried implementing a slew rate in your respective compositors?
<emersion>
nope
<zamundaaa[m]>
Not yet. I should be able to soon though
<doras>
zamundaaa: do you plan to scope it only to passively updating apps through some heuristic, or otherwise only in case of extreme changes in refresh rate?
<MrCooper>
doras: during the hackfest, Manasi mentioned that i915 developers are considering adding LFC, but there seemed to be consensus that we'd rather handle it in the Wayland compositor
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<zamundaaa[m]>
Dor Askayo: scope what? Slew rate limit has to happen whenever vrr is active
<doras>
MrCooper: I feel that we're missing opinions from people with knowledge about the kernel implementation of LFC for amdgpu.
<doras>
zamundaaa: so the second option I mentioned, then. The slew rate would kick in regardless and prevent extreme changes in refresh rate.
<doras>
I mean, you likely don't want the slew to affect the change in refresh rate in the case of small changes that wouldn't otherwise result in significant flicker. It would result in visual stutter in games (for example) without any benefit.
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<doras>
MrCooper: I'm asking these questions with VRR ranges between 1-N Hz in mind, where LFC won't ever be needed anyway.
<zamundaaa[m]>
Oh yeah, there's definitely different use cases for the default settings. I hope though that a properly configured maximum rate of change would work gor both
<zamundaaa[m]>
So that you limit change enough to prevent flicker but not so much that it makes it useless for games
<doras>
zamundaaa: yes, exactly
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<doras>
zamundaaa: how would you handle ramping refresh rate down? Send the same frame for presentation multiple times if necessary?
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<zamundaaa[m]>
Yes
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<karolherbst>
does any hardware have group operations on a workgroup level? Like all that subgroup stuff, just one level higher
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<Hazematman1>
OpenGL provoking vertex question. Is the provoking vertex supposed to affect the order in which vertices are processed during primitive assembly? I can't find any mention of this in the spec but I'm getting different behavior between different GPUs and the piglit test spec@!opengl 3.2@gl-3.2-adj-prims line cull-front pv-first seems to test for this
<cmichael>
this sounds oddly familiar ;)
<Hazematman1>
cmichael: Haha! When you're losing your mind trying to understand something you have to try and get all the help you can :P
<cmichael>
Hazematman1, oh I know that all too well ;)
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<mattst88>
eric_engestrom: I'd kind of forgotten about it, but would you mind making a release of glu as well?
<robclark>
does something about dma_fence confuse kmemleak? I've got a kmemleak report of a bunch of random fence leaks (and a few sync_file).. but it's a mix of drm/sched hw_fence and user_fence and kms atomic out-fence
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<tleydxdy>
at least some of those are real, I'm having a hard time tracking them down tho