ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<songafear>
If none wants to talk to me, i have perhaps problems to send out things to review, hence on the longer run, i would prefer to make a small presentation to the web, if xdc is not desured or possible, that could be some netmeeting conference, or just offline slides and or offline video presentation, that way it would be possible to rotate the head to the correct path on the development. I was not kidding at first i would love to talk with xorg crew as
<songafear>
to how to place the systems to the more modern end, ouh yeah i am mentally stable for some time already, lot of work was done mentally to be that.
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<hch12907>
gentle ping to issue #10185 (dev access to mesa/demos)?
<hch12907>
btw, I think giving all mesa/mesa developers the dev access to every other mesa repo (piglit, demos, ...) is a better solution overall.
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<karolherbst>
jenatali: ever looked into subgroup support for clon12?
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<jenatali>
karolherbst: not yet
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<karolherbst>
jenatali: sad... I was looking into openvino and apparently disabling subgroup support makes it work :')
<jenatali>
Oof
<jenatali>
karolherbst: does CL subgroup support require independent forward progress? Or is that something else?
<karolherbst>
only for cl_khr_subgroup
<karolherbst>
however.. intel came up with cl_intel_subgroups which is cl_khr_subgroups without independent forward progress (for pre CL 3.0) + a bunch of additional subgroup ops
<karolherbst>
they emulate the other ops
<karolherbst>
so that might be broken as well
<jenatali>
I see
<jenatali>
D3D doesn't have IFP guarantees. And I know that WARP can't do it for example
<karolherbst>
yeah.. you don't need IFP support to advertize subgroups in CL 3.0
<jenatali>
Any GPU that can run Nanite can do it though
<karolherbst>
it's only require for cl_khr_subgroups which is pre CL 3.0
<jenatali>
Oh cool. I need to do a full CL3.0 run and actually flip on that switch
<jenatali>
It's been a few years
<karolherbst>
I don't think the CL CTS actually tests it
<karolherbst>
just the API consistency bits
<karolherbst>
I think...
<karolherbst>
dunno :D
<karolherbst>
nvidia doesn't claim support for subgroups apparently....
<karolherbst>
mhh maybe opencl.gpuinfo is just weird
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<karolherbst>
mhh.. but on ROCm (which only advertizes cl_khr_subgroups) it works... maybe my implementation of subgroups is indeed a bit broken...
<karolherbst>
it also crashes the GPU with radeonsi... and disabling subgroups also makes it work there.. *sigh*
<karolherbst>
jenatali: do you know anything important which uses subgroups? Kinda want to test subgroup support with something else besides multi layer AI/ML stuff :D
<jenatali>
🤷
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<karolherbst>
sad
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<alyssa>
14:03 jenatali | Any GPU that can run Nanite can do it though
<alyssa>
cries in m1
<alyssa>
karolherbst: Is it expected to have to spill for large block sizes?
<alyssa>
=> is it expected that launch_grid might trigger a shader variant for variable block size?
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<karolherbst>
sadly yes
<alyssa>
ugh
<alyssa>
thanks
<karolherbst>
however
<karolherbst>
well.. not however
<karolherbst>
but you can pin the block size in CL
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<karolherbst>
reqd_work_group_size
<karolherbst>
and if that's set in the kenrel, it's illegal to launch it with a different local size
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<karolherbst>
alyssa: so you can e.g. compile all variants with specific `reqd_work_group_size` ahead of time and just use those...
<karolherbst>
could even have them all in the same source file
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<karolherbst>
and they just call into a common function
<alyssa>
whee.
<karolherbst>
`__attribute__((reqd_work_group_size(X, Y, Z))) ` on the kernel
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<pinchartl>
is anyone working on DP MST support for an ARM-based platform ?
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<HdkR>
pinchartl: Which ARM platform? I'm sure Tegras already support MST
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<HdkR>
The question is very broad
<pinchartl>
indeed
<pinchartl>
any platform that would use drm_bridge
<pinchartl>
so not tegra :-)
<pinchartl>
I was trying to find prior art and didn't see any in mainline or on the list
<pinchartl>
as far as I can see, only i915, nouveau and amdgpu have MST support
<songafear>
So only x86
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<songafear>
Weird, it's fun thing that MST
<pinchartl>
HdkR: I don't see any mention of MST in drivers/gpu/drm/tegra/
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<songafear>
You can easily control sync of the display mux by creating such control sync packets in the stream
<HdkR>
pinchartl: Oh sorry, newer tegra which should just use nouveau bits
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<HdkR>
Tegra the SoC rather than the drm API :)
<pinchartl>
:-)
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<songafear>
Yeah wau, so tegra has MST docks
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<HdkR>
Slap a radeon GPU in to an ARM device and we could technically claim that one is an ARM platform as well :P
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<songafear>
But how is the wire be split from the shared port?
<songafear>
To additional separate do ports right?
<songafear>
DP
<songafear>
do/dp
<songafear>
So it's analogue stream aggregation
<songafear>
And the packets flow through the data channel
<songafear>
So monitor or tv displays the stream of media
<songafear>
Data is av
<songafear>
Audio and video streams
<jenatali>
karolherbst: Kernels that came from CL C 1.2 (or are annotated a certain way) need to use a fixed grid size too, just not necessarily statically defined
<karolherbst>
there is no restriction on the grid size afaik
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<jenatali>
Just that it's fixed
<jenatali>
You can't have some work groups using different sizes than others. Varying work group size wasn't a thing until CL2
<karolherbst>
you mean block or grid?
<jenatali>
Er, block I gusss
<karolherbst>
yeah.. we were talking about the block size
<jenatali>
Sorry this terminology is foreign to me still
<karolherbst>
yeah...
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<karolherbst>
doesn't help that every vendor has different names either
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<karolherbst>
I think block/grid is what nvidia uses and where it comes from, but not sure
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<karolherbst>
maybe in the r600 days AMD used the same terms?
<jenatali>
Anyway, block size has to be uniform for CL1
<karolherbst>
dunno :)
<karolherbst>
yes
<karolherbst>
but it was about the block size specified through ndrangekernel
<karolherbst>
or I guess what the runtime picks for a given grid size...
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<jenatali>
Right, you just can't use a different size for the last block
<songafear>
It actually wasn't that you could not do that, just hw was not being controlled to run kernels on different cu's without restrictions, they could run only copies of kernels which were all same, no sync
<jenatali>
Which now that I re-read it, isn't what alyssa was asking about :)
<karolherbst>
:)
<alyssa>
(:
<songafear>
There were no synchronization primitives neither scheduling to control cu on various loads, you could though vary the block size in which case two streams run one kernel and five some other kernel and they would graduate together or something like this
<songafear>
But that's just one developers unimportant detail, it still works well for modern compute and graphics
<songafear>
But on all my chips I had best cl 2.1
<songafear>
Those are very good, cuda even also very good, single source
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<robclark>
pinchartl: some qc things support MST.. but not sure if anyone is working on that yet
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<pinchartl>
robclark: so someone will need to be the first to interface this with drm_bridge, and everybody is hoping someone else would do the work ? :-)
<robclark>
that is plausible
<pinchartl>
it wouldn't be a first
<pinchartl>
when that happens to me, if I wait long enough and the frustration builds up too much, it usually explodes in a desire to rewrite the whole subsystem
<pinchartl>
(I'm not very frustrated with DRM/KMS if anyone is wondering ;-))
<robclark>
tbh I'm not 100% sure why we need a bridge in that case (MST is only with external dp, no physical bridges involved.. but I've managed to avoid the dp code)
<pinchartl>
I've managed to avoid the MST code so far
<robclark>
maybe abhinav__ is aware of some plans on the mst side of things
<pinchartl>
wouldn't it be in theory feasible to have a DSI-to-DP bridge with MST support ?
<pinchartl>
DSI has virtual channels
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<pinchartl>
(not that I wish anyone would make such hardware)
<robclark>
idk.. probably.. but I've not seen it
<abhinav__>
pinchartl robclark we do have plans to add DP MST support , perhaps in the next 1-2 months. i can share more light on this that time
<pinchartl>
abhinav__: nice
<pinchartl>
well, before saying nice, I should wait to see how it looks like, and if it's one of those cases where the hardware designers should have stayed in bed on that fateful day
* pinchartl
should go to bed
<abhinav__>
pinchartl I will remember to CC you on the changes for DP MST when we post them
<pinchartl>
thank you
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