ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<MrCooper> enunes emersion: there's also the issue that dumb BOs aren't supposed to be usable for HW acceleration :)
<emersion> sure
<emersion> that's my original motivation for working on this
<MrCooper> cool
<emersion> eh, i just notice one leftover comment from old code
<emersion> will fix next version
<javierm> emersion, pq, sima: I've implemented what we discussed yesterday to fix the issue with FB_DAMAGE_CLIPS in virtio-gpu
<emersion> nice!
<javierm> emersion, pq, sima: it would be great if you can take a look to make sure that got it correctly: https://github.com/martinezjavier/linux/commits/drm-virtgpu-damage-fixes
<javierm> emersion: tested on weston in a VM, was able to reproduce the issue and with those patches the flickering goes away
<emersion> perfect
<emersion> that does full damage always in that case i'd assume
<emersion> (weston/wlroots/mutter case)
<javierm> emersion: in mutter it does not, but I guess that mutter doesn't use double buffering? Or at least I wasn't able to reproduce the artifacts with mutter
<emersion> if you have extra time, would be nice to (1) add a note/warning in the regular damage helper for driver devs about all of this
<emersion> (2) add TODOs
<emersion> mutter does use double buffering
<emersion> all modern userspace i know of does
<javierm> emersion: I see. Wonder why isn't visible there...
<emersion> probably because mutter submits an over-damaged region
<emersion> possibly a mutter bug
<emersion> (it could be that they mix up frame and buffer damage)
<emersion> (submit buffer damage, while kernel expects frame damage)
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<sima> javierm, clearing the damage rects feels a bit like a hack, I'd have set iter->full_damage instead
<sima> so that you have both a buffer_damage_iter and buffer_damage_merged version
<sima> and wouldn't need to open-code in vmwgfx
<sima> but ... eh, not feeling very strongly on this
<sima> javierm, the one I'd really like to see though is a doc patch adding links to the two buffer vs frame damage graphs we discussed yesterday
<sima> and then maybe in that section also link to the 2 set of different functions
<javierm> sima: sure, I'll add that. And also the TODO and note that emersion suggested
<sima> also I think the 2 set of functions should link to the other type with a "if your driver needs buffer/frame damage instead", which is maybe a better reason to roll out the full symmetric uapi
<sima> javierm, but wrt the uapi logic, I think you have the right if condition
<javierm> emersion: the TODO is what pq mentioned, right?
<sima> javierm, I also wonder whether there's a good place to put down the rule of thumb/summary I typed yesterday on irc, maybe in the damage helper DOC: section?
<javierm> < pq>| if it's per-buffer, you also need "buffer age" or similar damage accumulation algorithm
<emersion> the TODO is do something smarter than full-damage when FB_ID changes
<sima> I mean the upload target rule: per-plane/crtc->frame damage, per-fb/bo->buffer damage
<emersion> yeah, accumulating damage in a ring buffer
<javierm> emersion: thanks. Just wanted to make sure I got that correctly. I'll do that then, thanks!
<emersion> ty :)
<sima> yeah TODO for buffer age/damage accumulation would be good, maybe could put that into the DOC: overview?
<javierm> sima: Ok, I'll figure out how to add that content in the docs
<javierm> sima: about clearing FB_DAMAGE_CLIPS vs settting iter->full_damage = true, the problem is that with the latter we will need a custom iter_init
<javierm> and wanted to keep the change minimal so that could be backported as a fix...
<sima> javierm, yeah
<javierm> sima: maybe we could go with this approach and then refactor?
<sima> javierm, adding a custom iter_init is imo still well within backport rules
<javierm> sima: yes, but the driver is using the helper that does both
<sima> javierm, I wouldn't, this is tricky enough that a special backport patch version doesn't sound like a good idea
<javierm> so would have to duplicate the logic and couldn't reuse it
<sima> like gregkh really doesn't like custom backports ...
<javierm> sima: yes, that's why I thought the patches would be minimal and applied cleanly for v6.5
<sima> hm
<sima> javierm, so I think buffer_damage_iter_init could just call iter_init and then adjust like you do?
<sima> and for damage_merged I guess you'd need a __damage_merged with a (bool buffer_damage)
<sima> that doesn't look too horrendous
<sima> and should be still within stable limits (if we ignore the documentation part)
<javierm> sima: yeah, that's what I had but felt like a bigger change. I'll do that though if you prefer and is withing backporting rules
<sima> I think it's within, and the symmetry I think wins us enough in documentation clarity that it's justified ...
<javierm> sima: got it. Will do that
<sima> javierm, if you want to, I guess you could split out the doc patch (since damage helpers don't have a DOC: section yet)
<sima> and not mark that for cc: stable ...
<sima> but ... *shrug*
<javierm> sima: yeah, I was going to only add Fixes: to the helper + virtio-gpu patches and only Cc stable on those
<sima> yeah
<javierm> not even for the vmwgfx, nobody reported nothing for that one :)
<sima> and then a patch to add a DOC: section explaining the frame vs buffer damage and which sets of helpers you want in each
<javierm> sima: sure
<sima> javierm, I guess/hope that when you send it out vmwgfx folks hopefully test and apply themselves
<sima> since it's really not great when we have inconsistent uapi like this
<javierm> agreed
<sima> javierm, also might be a good idea to raise a mutter issue, if that one does indeed do buffer damage and not frame damage?
<javierm> sima: yes, I'll discuss with the mutter folks
<sima> might need a bit care to make sure the fixes have hit enough stable kernels and distros ...
<javierm> sima: I'm not worried because mutter has virtio-gpu (and vmwgfx) is a atomic KMS deny list, I've a local patch to test damage handling there
<javierm> *in a
<javierm> the reason for this is that the cursor hotspots patches haven't landed yet
<emersion> > the Pi5 will have multiple display nodes (4(?) iirc) with different capabilities, vc4 being only one of them
<emersion> oh. boy.
<emersion> daniels ^ you knew about this?
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<sima> glorious
<sima> re pi5
<javierm> sima, emersion, pq: thanks again for your time and explanations, I learned a ton about frame vs buffer damage. I need to do some $dayjob taks but will post the patches later today :)
<emersion> javierm: glad i could help, thanks for all of the fixes and mess cleanup! :D
<emersion> now i think i really need to order a RPI5
<emersion> moar exotic setups
<daniels> emersion: lots of fun for us all :\
<sima> tell me they managed to create the most cursed venn diagrams of tiling modes
<sima> like 3 ip blocks, only joint formats between each pair
<sima> or something like that
<emersion> did they manage to outdo NVIDIA (can't render to LINEAR)?
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<emersion> mripard: if you have more details about the RPi 5 display nodes i'd be interested
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<mripard> did you have a coffee yet ? :)
* emersion grabs popcorn
<mripard> so, the basic idea is that they stripped MIPI-DSI, MIPI-DPI and analog TV out of the SoC (and thus vc4) and into a discrete PCIe chip
<mripard> vc4 only has writeback and HDMI now
<mripard> the RP-1 is that PCIe chip and has a public documentation
<emersion> hm
<emersion> in terms of tiling and memory requirements for scanout, do you know what's up?
<mripard> yes, they only support XRGB8888 iirc
<emersion> LINEAR?
<sima> weeeeeeeee
<mripard> that's my understanding
<sima> vram?
<emersion> can you allocate CMA and scanout on the PCIe thing?
<mripard> so if you want to output any format output by the GPU or codec in hardware, you have to go through vc4, use the writeback to convert it to XRGB, and use that
<emersion> or does the PCIe thing have its own scanout memory?
<emersion> ugh
<mripard> no, there's no VRAM
<mripard> so it's all in RAM afaik
<emersion> do you *have* to go through writeback, or can you use GL/Vulkan instead?
<mripard> I was only involved on vc4, so that part is a bit blurry to me, sorry
<emersion> okok
<mripard> no, you don't need to, so as long as you have the proper shaders to convert whatever tiled YUV you have to XRGB, it should work just fine
<emersion> ok, that makes it easier for user-space
<emersion> so they use writeback as a 2D API lol
<mripard> I don't know if they do at the moment, but we discussed it at some point
<sima> I guess bit less memory bw at the cost of the external displays being one frame behind?
<mripard> the good thing is that it puts us pretty much in the same spot than SPI/I2C displays, so javierm is going to be super happy about whatever comes out of it :)
<mripard> sima: yeah, and also less power consumption if using writeback I assume
<javierm> mripard: haha
<sima> mripard, if they can scan out directly from system memory it's a lot better than most spi/i2c
<sima> otoh lack of framebuffer compression in a modern soc ... ugh
<mripard> sima: sure, I was talking about the formats mismatch between the GPU/codec output and what the display device supports
<sima> also pcie in your scanout path ... I do not pity the poor soul who has to figure out the watermarks for the fifos
<sima> afaik no one has tried that yet
<mripard> sima: "Framebuffer compression is for those who can't build a memory bus" or something
<sima> mripard, yeah, except I don't think there's anyone else than apple who can build a memory bus for a mobile/laptop soc :-P
<sima> and they also still have compression
<sima> mripard, I guess the plan is to instantiate all the devices with dt, because really it's just an arm soc?
<sima> behind the pcie device I mean
<mripard> I think it's all enumerated?
<sima> oh really?
<mripard> like I said, I wasn't really involved on that part, but that was my assumption because it's PCIe
<sima> I've seen a few of these "whack a soc behind a pcie bridge" designs, and they're all just "here's a pci bar for the entire thing, good luck"
<sima> so would be really suprising if it's all properly enumerated as pci functions
<emersion> mupuf, if you have a RPi 5 running with their stack, i'd be interested in a drm_info dump
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<sima> mripard, well that's just for the display, kinda makes sense to keep that
<mripard> and it's indeed DT based devices
<sima> I was wondering about all the devices on the soc, since I guess we have drivers for a lot of them already with dt bindings ...
<sima> mripard, ah neat
<sima> yeah just found the of matches
<kode54> Oh right, I need to supply new drm info dump, even if my hardware is less rare now
<kode54> (6700 XT, bet you have dumps of those already)
<lynxeye> sima: On DT platforms you can simply describe the soc behind the bar via the usual DT means. No idea if Rpi actually does this.
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<sima> lynxeye, oh so you just have the dt for behind the pcie bar in your overall soc dt?
<sima> (it's a separate pcie chip here)
<mripard> it looks like it's what they do
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<sima> this feels like it would break gregkh ...
<lynxeye> sima: yep, describe the PCIe endpoint below below the RC in your SoC DT, add DT devices as child devices of your PCIe endpoint.
<mripard> sima: I'm sure you didn't meet the USB devices binding yet :)
<sima> well I guess it's better than the x86 approach of just having random mmio window mirrored into everything, because a driver on windows cannot access anything outside of its pcie bar ...
<sima> (and then the chip/fw dies because there's races)
<javierm> lynxeye, sima, mripard: I guess the DT binding could be similar to the ChromeOS Embedded Controllers that have peripherals behind it:
<lynxeye> sima: x86 with its fixed ACPI tables in firmware and "driver needs to know how the complex HW behind a PCI ID looks like" just feels awkward as soon as you got sufficiently deep into the DT rabbit hole ;)
<javierm> this is a EC in a SPI bus that exposes an I2C tunnel
<sima> lynxeye, oh it's very awkward
<sima> but mostly it's awkward because windows driver model is crap
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<pq> javierm, you're welcome. :-)
<pq> emersion, writeback as a 2D hardware composition API... and color pipelines incoming. We might actually get a proper 2D API in a decade or two. :-D
<emersion> yeah… not sure KMS is a super great API for 2D blitters but oh well
<javierm> everything old is new again :)
<mripard> if only :)
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<mupuf> emersion:
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<mupuf> emersion: this time with the message: will do when I get to it. It's not the highest priority right now ;)
<emersion> mupuf: ty, yeah, no problem at all
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<Company> MrCooper: re our discussion about zmike's blog post
<Company> "After a successful return [of vkAcquireNextImageKHR()], the image indicated by pImageIndex and its data will be unmodified compared to when it was presented."
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<javierm> sima, emersion: I guess that https://docs.kernel.org/gpu/drm-kms.html#damage-tracking-properties is a good place to put that buffer vs frame damage explanation and links ?
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<emersion> probably yeah
<javierm> emersion: Ok
<emersion> and link to it from the functions
<emersion> ideally
<emersion> ask me if you don't know how to link (took me a while to figure out)
<javierm> emersion: yeah, I was planning to do that and also in the TODO
<javierm> emersion: perfect, will do
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<kj> For isaspec, what would be the correct way to go about a case where all but one instruction has a specific bit used for a paricular function?
<kj> I've defined the field in the top most bitset and then used an override in the special case, with an expr that's always true, and provided an "x" pattern as the alternative to the override
<kj> Not sure if that's the correct way of doing it, or if there's a better way, without having the field defined in each instruction separately
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<danylo> kj Alternatively you could add one more level of inheritance and place that field there. You also could probably move override to the base definition and use params to enable it
<danylo> But for a single edge case I guess your way is as good as any
<kj> Thanks. I'll have a look into how params work then
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<MrCooper> Company: that makes more sense, thanks
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<Company> at least all the spec binging is finally good for something!
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<mupuf> emersion: ready for 16K memory pages on the Pi 5?
<mupuf> marcan won't feel alone anymore :D
<emersion> wew
<karolherbst> I wonder how long we'll keep the page size a compile time option...
<emersion> considering how many places assume it's a constant? probably a very long time
<karolherbst> I meant on the kernel side tho
<emersion> yea
<karolherbst> so userspace can either run in 4k or 16k or 64k mode or whatever
<karolherbst> but yeah...
<karolherbst> it's a massive project to make it all a runtime thing
<emersion> sysconf(PAGESIZE) -- wonder how many user-space programs do that
<karolherbst> <1%
<emersion> optimistic!
<karolherbst> `#define PAGE_SIZE sysconf(PAGESIZE)` ez fix
<emersion> ahah
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<karolherbst> but yeah.. I think the idea of turning it dynamic on the kernel side was shot down a few times "due to performance regressions"
<karolherbst> so yeah...
<MrCooper> folios seem to provide a lot of the same benefits
<jani> mripard: mlankhorst: tzimmermann_: ack? https://lore.kernel.org/r/877cn04hvq.fsf@intel.com
<mripard> jani: ack
<jani> mripard: thanks!
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<javierm> sima, tzimmermann_: what's the difference between "Subsystem-wide refactorings" and "Core refactorings" sections in Documentation/gpu/todo.rst ?
<javierm> I would had thought the later is for refactoring that don't affect drivers and the former if core + driver changes are needed? But the items in each seems to be inconsistent in that regard
<javierm> trying to figure out in which one should fall the "Implement buffer age or other damage accumulation algorithm for buffer damage handling" item
<javierm> emersion: ^
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<emersion> hm i wouldn't call it a refactoring
<javierm> emersion: yeah me neither but that's how is divided the TODO doc...
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<javierm> should I add a new section then?
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<javierm> there's also "Driver Specific", maybe there?
<javierm> emersion: hmm, "Bootsplash" and "Brightness handling on devices with multiple internal panels" also have their own sections, I'll add another one then
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<tzimmermann> javierm, idk
<jani> mripard: aww crap. asked for ack, got ack, forgot to record it in the commit messages *facepalm*
<mripard> jani: don't worry about it :)
<jani> mripard: thanks :)
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<enunes> emersion daniels so on rpi4 the main device we get from dmabuf feedback in the client is always the gpu render device, and at first we get only tranches still with the gpu device as target devices too, only a bit later we do get a target tranche with the display drm device
<enunes> it seems to be ok as the only tranche with the scanout flag is the target tranche with the display drm device
<emersion> yeah that's expected
<enunes> that info is not passed all the way to the device though, so I guess I need to store it in device specific data so its accessible at the time we do v3dv_AllocateMemory
<emersion> we need to stash it somewhere just like we stash the modifier list
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<enunes[m]> zamundaaa @zamundaaa:kde.org: I guess it will be ok as long as it sends the proper device and scanout flags in the target tranches (btw I only got your message on matrix not irc)
<zamundaaa[m]> Ok. Yeah the IRC bridge went down / restarted / whatever today again. This message should get through
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<emersion> it did
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<kiroma> Hey, I've gotten myself recently an ARM board and wanted to try contributing to Mesa, what's usually used to test for breakages between patches?
<HdkR> piglit and Khronos CTS
<HdkR> Which are a nice suite of test cases to ensure the world doesn't break :)
<kiroma> Oh, piglit is a wee bit... large