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<MasterR3C0RD>
On second glance, it looks like they just copied the code from another driver or something. In any case, I don't see a driver for it anywhere else, and I can't find even implications of a datasheet for it
<parthiban>
MasterR3C0RD: Moin! I have TCS4838 in my custom PCB as well. Tied over I2C.
<MasterR3C0RD>
Would you happen to have a datasheet for it?
<MasterR3C0RD>
It looks like its closest match is the SY8827G, which according to that driver there seems to potentially only differ with its minimum voltage
<parthiban>
I remember looking at this datasheet in the past. But couldn't locate in my machine now.
<parthiban>
But should be able to get it from the maker of this PCB.
<parthiban>
All under drivers/power/mfd/pmu-ext-i2c.c
<parthiban>
IDK I see VDD-CPU is combing from both AXP717C LX1_1 and also TCS4838 SW_x.
<MasterR3C0RD>
I don't have anything to work off of for schematics sadly; all I know for sure is that this seems to have an AXP2202 and a TCS4838; cpu-supply is tcs4838-dcdc0 and potentially dcdc0 and dcdc1 are polyphased to supply CPU power
<MasterR3C0RD>
As dcdc1 is defined to the same min/max-microvolt but only dcdc0 is always-on/boot-on, and dcdc1 isn't referenced
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<warpme>
MasterR3C0RD : fyi: i built & tried syterkit with all variants of t527 on mine h728. None will go :-( This is because all syterkit supported boards are lpddr4 while mine h728 box is ddr3. So effectively i'm on your hands regarding booting h728....
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<theslowcoder>
Jookia: I finally managed to get I2C working on the T113-S3. Turns out, I'm an idiot, and can't spell "pinctrl"...
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<MasterR3C0RD>
warpme: I haven't looked too closely, but you should be able to set the DRAM parameters and such for your board
<MasterR3C0RD>
You'll have to do so anyways for U-Boot; I think the primary difference is that SyterKit has the configuration data in its code, but it's in a struct that should be easy to edit
<warpme>
MasterR3C0RD : yeah i also think to use a523 code with ddr3 dram code implanted from other (ddr3) board. not sure du syterkit has any aw board with ddr3....
<MasterR3C0RD>
The DRAM code used by SyterKit does support DDR3 I believe; its payload is what I'll be using for reverse engineering so
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<parthiban>
MasterR3C0RD apritzel I will have some time left during next week. So am planning to start TF-A for A133. Am new to TF-A, looking at H616 and past commits, it's mostly playing around with plat/allwinner directory it seems. Any hints and pointers will be helpful. Thanks.
<parthiban>
MasterR3C0RD also on the display side, I tried DSI quickly with de0 + tcon0 today, although the panel is added fine (which am not sure yet as this panel is not in the upstream yet), kernel failed bind the DSI parts. I need to have closer look in the clocks.
<parthiban>
On the GPU front, with the help of #powervr community, managed to get vulkaninfo working with the GPU. But not able to run any real display applications still.
<MasterR3C0RD>
parthiban: Sounds like progress at least! I'll take a look this weekend at fixing that last address mapping bug you're running into with the new code (assuming it's the same relocation failure as before)
<parthiban>
Great, thanks.
<MasterR3C0RD>
But once that's working I should have a base to work off of for the H616/A133/A523 "combo" DRAM driver
<parthiban>
All three SoC's using the same DRAM controller and PHY?
<MasterR3C0RD>
Same controller, PHY is almost exactly the same between A133/H616, and A523 has some differences with some registers being packed but is also otherwise identical from the looks of it
<MasterR3C0RD>
Controller layer at least is shared, COMMON block code between H616 and A523 should be portable, and PHY can share structure at worst
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<MasterR3C0RD>
I'll mainly just need to figure out how I want to structure the H616 refactor bits; mainly I will want to move the H616 driver into drivers/dram, whilst moving its config parameters over as well. Then figure out a "name" for the driver
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<MasterR3C0RD>
And then I already have some concepts I'd like to look at post-refactor, though I haven't yet studied to see if they'd even be feasible (size/arch constraints); for example, I could see DRAM parameters being defined in the device tree
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