<Jookia>
im considering sending a documentation patch to clarify that the DE flags mean mixer flags and the datasheet is wrong with my next tcon revision
<Jookia>
but i also don't know, the tcon top patch series is stalled until someone clarifies what is actually happening in the driver
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<Jookia>
hardware*
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<parthiban>
Jookia: I may be wrong. But with DE = mixer, A133 is different as DE1 is placed in different memory map. Also the manual didn't mention anything related to DE1. So I agree considering 2 x RT mixer will be 2 DE's technically.
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<warpme>
apritzel : your work was key enabler for this! milion thx!
<warpme>
6.12
<apritzel>
glad that it worked!
<apritzel>
and I found some update image for the X96Q Pro+ and checked the DTB: according to that there are two PMICs
<apritzel>
this error in your log is odd, though: 0x40 should be writeable
<warpme>
ah great to know!. i'll apply it for sure. also dt is from avaota and i need to develop correct one basing on android dts have. But key thing is: mainline boot to stage where further works is possible :-)
<warpme>
pmic: yes: 717 and 323. currently (due wrong dt) sd card not works (probably 323 pmic has wrong setup)
<apritzel>
warpme: the 717 did not probe, because of this error. So everything that uses one of the main PMIC rails will probably not work
<apritzel>
which includes the main pinctrl, USB, and even serial, hence you don't see further output
<warpme>
yes indeed
<apritzel>
curious why access to IRQ0_EN (0x40) provokes an -ENXIO, though
<apritzel>
ah, I was wondering already about the I2C address: looks like it's using 0x34 instead of 0x35 on the Avaota
<warpme>
qll. perfect catch!
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<paulk>
btw I'd be curious to get people's opinion on this default irq debouncing limit at 32 khz
<paulk>
it seems pretty clear to me that keeping the register default breaks many uses cases (high-speed sampling as well as short less frequent interrupts)
<paulk>
while it's only beneficial for broken hardware that might generate irq storms
<paulk>
for which a device-tree property can be used to lower the debouncing period
<paulk>
also 32 khz is just the source clock rate, it may in fact need multiple periods (it's unclear how many) to detect an interrupt, so the actual filter frequency is probably somewhere in 1-16 khz
<apritzel>
are interrupt storms from GPIO IRQs an actual argument someone observed and brought up? Sounds quite constructed to me ...
<apritzel>
in general I believe a real problem to fix trumps theoretical considerations
<apritzel>
(I need to look at the patch in detail, just my first thoughts)
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<paulk>
apritzel: see the mailing thread indeed
<paulk>
I don't think this has been observed in practice
<paulk>
my use case however was that irqs from a common sparkfun sensor breakout board were completely invisible because it's asserted for a short time
<paulk>
also there are many ways to handle possible IRQ storms that don't require breaking other uses cases
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<Jookia>
it kind of sucks that all the people that needed my tcon fix patch have disappeared :\
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<apritzel>
Jookia: again you are way too impatient for this whole OS business ;-)
<Jookia>
apritzel: yeah, i guess so
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