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<apritzel> that's probably coming from the RTC clock part, that gates and controls the LOSC
<apritzel> not sure we have that part for the A100 yet
<apritzel> X32KFOUT is the name for that used in the manual
<apritzel> roughly "oscillator 32KHz fan out"
<MasterR3C0RD> Looks like I should dig into that then
<apritzel> in the DT that would be <&rtc CLK_OSC32K_FANOUT>, provided by ccu-sun6i-rtc.c
<apritzel> I think the original A100 patches might predate this driver
<apritzel> ouch, we actually don't support the RTC at all? that's quite bad - not so much for the calendar, but for the clocks it controls
<apritzel> because any device taking the osc32k clock should actually refer to the RTC, which controls the internal LOSC clock
<apritzel> which means that would break DT compatibility, because older kernels don't know about this device
<MasterR3C0RD> Perhaps that explains some of our clock issues?
<apritzel> I don't think so, because the gate is open normally. It's actually more a technicality to route it through the RTC device, because it's the correct way to describe the hardware
<apritzel> s/because it's the correct way/but it's the correct way/
<apritzel> I think for enabling the fanout signal you need the RTC driver, though: someone needs to set bit0 in register +0x60
<apritzel> MasterR3C0RD: check sun50i-h618-transpeed-8k618-t.dts for an example
<MasterR3C0RD> I'll see if I can get away with just using a H616 compatible for now
<apritzel> as a hack maybe, but by experience the clock part of the RTCs typically differ by details
<MasterR3C0RD> Actually, it seems closer to the H3's RTC; prescaler of 32 with additional configurable prescaler, with 16MHz RC, and has_out_clk
<MasterR3C0RD> Even closer to the H6; losc_en and auto switch
<MasterR3C0RD> Only difference is that there's only one alarm instead of two
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<apritzel> please note that the clock part and the calendar/RTC part are in different drivers, at least for newer SoCs
<MasterR3C0RD> Yeah I'm starting to see that it is closer to the H6, it's just that the clocks don't seem to have parents in the vendor tree
<MasterR3C0RD> *H616
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<MasterR3C0RD> By extension, so does the RTC of course, but I can't properly test that on a device without an RTC battery
<MasterR3C0RD> Test it thoroughly I mean
<parthiban> apritzel: MasterR3C0RD: Morning!
<parthiban> apritzel: peekpoke thanks for that. I will try reading the registers using that.
<parthiban> MasterR3C0RD: WLAN works in SDIO? In my case, I have a dedicated cryptal for low freq 32k.
<MasterR3C0RD> parthiban: Yep! I'm preparing some patches that do the work I just completed; will post here once they're ready
<parthiban> Are there any changes for MMC?
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<MasterR3C0RD> Nothing yet, no
<parthiban> Surprise then. I thought the SD clock problem and SDIO WLAN loading in my case was related. May be not.
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<MasterR3C0RD> parthiban: Is the 32kHz crystal going directly into the WiFi chip or does it go into the A133 first?
<MasterR3C0RD> Also I didn't realize today was the end of DST; got confused why my message got sent in the past LOL
<parthiban> MasterR3C0RD: Coming from X32KFOUT (U3) and also from the crystal. That's confusing. There must be DNP resistor in the schematocs which am missing.
<parthiban> So the problem is LPO 32K is not enabled? I think this needs an fixed-clock entry in the DTS.
<MasterR3C0RD> It needs more than that; losc is managed by the RTC on Allwinner chips
<MasterR3C0RD> As is the LOSC fanout/output pin
<parthiban> So we need the RTC enabled.
<MasterR3C0RD> Yes, it's a simple set of patches luckily
<parthiban> Btw, display pipeline in A133 is unique. mixer <-> tcon_top <-> lcd/lvds
<parthiban> tcon_top supports only tv, dsi
<MasterR3C0RD> Ahh, that likely explains why there's a different low level file for it
<parthiban> Which one? lowlevel_v2x/ ?
<MasterR3C0RD> Yeah, there's one specific to sun50iw10p1 (A100 series)
<parthiban> I still don't get the reference for the existing tcon_top implementation in upstream.
<parthiban> DE 2.0 or 3.0 specification doesn't have this details either.
<MasterR3C0RD> In mainline I'm pretty sure it's all referenced with mixer inputs/outputs to the different modules
<parthiban> Am referring to drivers/gpu/drm/sun4i/sun8i_tcon_top.h
<parthiban> I don't know where these register details coming from actually.
<MasterR3C0RD> I would assume someone found a source on it at some point, or referred to a vendor tree
<parthiban> MasterR3C0RD: You are right. R40 manual states these details.
<MasterR3C0RD> Double checking my non-hacky RTC fixes work and pushing them up shortly...
<parthiban> I will try them for my WiFi after display works
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<MasterR3C0RD> parthiban: Might be a silly question you don't know the answer to, but do you know what properties the `regulator-step-delay-us` and `regulator-final-delay-us` map to in mainline?
<MasterR3C0RD> On the regulators
<parthiban> Not sure. May be startup-delay-us
<parthiban> Datasheet should say whether it's ramping delay or start / on-off one
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<MasterR3C0RD> Can't see any reference to the delays in the datasheet, but I'm going to guess they map somewhat to regulator-ramp-delay and regulator-enable-ramp-delay
<parthiban> There is no timing diagram in the regulator datasheet?
<parthiban> Oh, for the PMIC. It should be ramp
<parthiban> Also should be configurable AFAIK
<MasterR3C0RD> Alright, I pushed a new branch, allwinner-a100-stage3
<MasterR3C0RD> parthiban: This has the RTC driver and DTS updates to get LOSC_FANOUT working
<MasterR3C0RD> If you have anything using iosc or losc/osc32k in your tree, you'll need to update those references so they refer to <&rtc CLK_IOSC> and <&rtc CLK_OSC32K> respectively
<MasterR3C0RD> Fanout is <&rtc CLK_OSC32K_FANOUT>
<parthiban> Thanks
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<MasterR3C0RD> Oh, and to define your external osc, you'd simply update the "rtc" binding and add to the clock using name "ext-osc32k"
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<MasterR3C0RD> parthiban: https://i.ibb.co/W2nL65Z/image.png
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<parthiban> MasterR3C0RD: Great. Now you can do scp to SD card for quick dev
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<MasterR3C0RD> Ethernet's just about working, I have the PHY coming up now. Not getting an IP yet, but I have blinkenlights on the ethernet port (which actually didn't happen on the stock firmware, oddly enough), and it's certainly trying to do DHCP
<MasterR3C0RD> The PHY also shows up in mdio-tools
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<MasterR3C0RD> Hmm, it starts up fine, I can talk to it using MMIO and MII, and link status is set, but it doesn't look like I'm sending packets. Also I can't seem to negotiate 1Gbps, though that might be things bugging out
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