<jernej>
apritzel: very nice series! iirc you said that you also work on better clock management for U-Boot proper?
Schimsalabim has quit [Ping timeout: 480 seconds]
Schimsalabim has joined #linux-sunxi
cnxsoft1 has joined #linux-sunxi
cnxsoft has quit [Ping timeout: 480 seconds]
cnxsoft has joined #linux-sunxi
cnxsoft1 has quit [Ping timeout: 480 seconds]
cnxsoft has quit [Ping timeout: 480 seconds]
warpme has joined #linux-sunxi
warpme has quit []
montjoie_ is now known as montjoie
<montjoie>
when merged, I will add my radxa board to kernelci
apritzel has joined #linux-sunxi
warpme has joined #linux-sunxi
warpme has quit [Ping timeout: 480 seconds]
apritzel has quit [Ping timeout: 480 seconds]
vagrantc has joined #linux-sunxi
tlwoerner has quit [Quit: Leaving]
psydroid has quit [Ping timeout: 480 seconds]
psydroid has joined #linux-sunxi
ftg has joined #linux-sunxi
apritzel has joined #linux-sunxi
vagrantc has quit [Quit: leaving]
apritzel has quit [Ping timeout: 480 seconds]
warpme has joined #linux-sunxi
JohnDoe0 has quit []
warpme has quit []
warpme has joined #linux-sunxi
warpme has quit []
warpme has joined #linux-sunxi
warpme has quit []
Schimsalabim has quit [Read error: Connection reset by peer]
Schimsalabim has joined #linux-sunxi
gsz has quit [Ping timeout: 480 seconds]
apritzel has joined #linux-sunxi
Raqbit339890 has quit []
Raqbit339890 has joined #linux-sunxi
ftg^ has joined #linux-sunxi
ftg has quit [Ping timeout: 480 seconds]
<apritzel>
jernej: thanks! Though "nice" is not the first thing that comes to my mind, it's more "massive" and "annoying" ;-) But I guess we have to just get through this ...
<apritzel>
and many thanks for the reviews, much appreciated!
<apritzel>
jernej: do I get this correctly, that the mode registers are registers in the DRAM *chips*, specified by JEDEC (per DDR generation), and set general access strategies (burst length, etc), so are not board specific?
<apritzel>
so in the DRAM init code we decide on which features we want, then program them. It's just that their meaning and encoding differs between DRAM generations, so we have to use values specific to DDR3, LPDDR4, ...?
<apritzel>
jernej: oh, and regarding the new clock code: I have some easy code to implement clock_set_rate() for a few clocks on the A64, without boiling the ocean and pulling in all of the Linux infrastructure
<apritzel>
this is purely for the video PLLs at the moment, I don't think we will need much more. For MMC we need (non-DM) SPL support anyway, so can just keep using the old code