<dansan>
So I've noticed heavy use of eval in OpenWRT core scripts (/lib/functions.sh, etc.) and avoidance of subshells. Is eval more efficient for setting variables than using subshells?
rua has quit [Ping timeout: 480 seconds]
rua has joined #openwrt-devel
csrf has quit [Ping timeout: 480 seconds]
minimal has quit [Quit: Leaving]
srslypascal is now known as Guest2734
srslypascal has joined #openwrt-devel
Guest2734 has quit [Ping timeout: 480 seconds]
rua has quit [Ping timeout: 480 seconds]
cmonroe has quit [Ping timeout: 480 seconds]
csrf has joined #openwrt-devel
danitool has quit [Quit: Cubum autem in duos cubos, aut quadratoquadratum in duos quadratoquadratos]
cmonroe has joined #openwrt-devel
rua has joined #openwrt-devel
noltari has quit [Quit: Bye ~ Happy Hacking!]
noltari has joined #openwrt-devel
guidosarducci has quit [Remote host closed the connection]
guidosarducci has joined #openwrt-devel
srslypascal has quit [Remote host closed the connection]
srslypascal has joined #openwrt-devel
csrf has quit [Ping timeout: 480 seconds]
ekathva has joined #openwrt-devel
csrf has joined #openwrt-devel
csrf has quit [Ping timeout: 480 seconds]
csharper2005 has quit [Remote host closed the connection]
rmilecki has quit [Remote host closed the connection]
rmilecki has joined #openwrt-devel
rua has quit [Ping timeout: 480 seconds]
rua has joined #openwrt-devel
ecloud_ has quit [Ping timeout: 480 seconds]
cbeznea has joined #openwrt-devel
dgcampea has quit [Remote host closed the connection]
<aiyion>
I'm just running out of ideas how to get it on the flash ...
<aiyion>
the DNA-load did not work either.
<aiyion>
Not sure if there's something I'm missing; I shortened the name of the file to something like firmwareinit.bin to be shorter than 64 chars
fblaese has joined #openwrt-devel
<neggles>
I don't know why I didn't think of this sooner
<neggles>
but i am into a firebox T20 now
<neggles>
hey watchguard, pro tip: if you're going to put a password on u-boot you might want to actually use secure boot
<dwfreed>
rofl
<dwfreed>
did they put the password in env, or just not forbid overwriting the uboot image?
<aiyion>
no signs of tftp bootmode when one resets the device...
<aiyion>
loading to partition two also fails.
<aiyion>
PaulFertser: if you could let me know how you flashed your revision R device, I'd be pretty happy -.-Ä
<neggles>
dwfreed: it's not in env, they wrote a little u-boot app
<neggles>
ghidra does a terrible job of disassembling it, and so far they've dragged their feet on giving me/stintel GPL sources for about six months, so i've no clue how it's generating it - but it's 32 characters long and generated based on several bits of system info
T-Bone has joined #openwrt-devel
<neggles>
iirc it concats the serial and mac together then does a bunch of BS with bit shifts and base64 conversions
<neggles>
time to hack up a kernel+initramfs i can boot
<dwfreed>
neggles: nice
f00b4r0 has quit [Ping timeout: 480 seconds]
<neggles>
none of the usual init=/bin/sh etc. tricks seem to work grr
<neggles>
the command line gets passed
<neggles>
but it ignores it :(
<dwfreed>
I mean, just like openwrt :)
<aiyion>
ffs. connecting the serial port like described in the wiki just fried my ch341a.
<neggles>
dwfreed: only on devices with cmdline override :P
<neggles>
aiyion: i would be using snapshot or 22.03 rather than 21.02.3 on those devices
<neggles>
and if you connected 3.3V to your CH341 that'd be the problem
<neggles>
dwfreed: https://paste.neggles.dev/xEtXq they have some hacky bastard lovechild of systemd and sysV-init going on here
<aiyion>
neggles: connected rx, tx and gnd if thw wiki page tells the truth. I haven't got a multimeter on this site to verify it.
<neggles>
aiyion: J10 yeah?
<aiyion>
but sure, I'll give 22.03 a try as well
<aiyion>
J3?
<neggles>
sorry
<neggles>
J8
<neggles>
i misread
<aiyion>
"
<aiyion>
J10 is an SWD header to program the Nuvoton Chip.
<aiyion>
J8 is to control POE.
<aiyion>
J9...
<neggles>
wiki says J9 is PoE
<aiyion>
I'm not trying to connect to PoE; I'd like to get openwrt on this pleasent device.
<dwfreed>
neggles: I don't see any mention of systemd there?
<neggles>
yes'm, so that should be J8
<aiyion>
That would be via Soc UART in J3
<aiyion>
Or not?
<neggles>
wiki says J8 but someone could've misread
<neggles>
dwfreed: it's brought up quietly in the background by watchguard's own stuff
<aiyion>
which wiki?
<neggles>
that page
<neggles>
oh
<neggles>
no
<neggles>
*I* am the blind one yikes
<neggles>
that is a 3, not an 8
<aiyion>
nice, thanks though.
<neggles>
also, in my defense
<neggles>
A Serial header is found at J8. Pins are Vcc(3.3V, Square), TX, RX and GND. Serial connection is via 115200 baud, 8N1.
<neggles>
then the 'pin-outs' bit has J3
<aiyion>
jep
<neggles>
so, typo :P
<aiyion>
...
<dwfreed>
neggles: gross
<neggles>
anyway. if you've got it oriented with the ports facing towards you (same as in the pic) it should be 3V3, TX, RX, GND, so <don't connect>, UART adapter RX, UART adapter TX, GND
<aiyion>
holy crap.
<aiyion>
j8 is populated.
<neggles>
is it? I can't even see it in the pic
<aiyion>
on my device it is.
<aiyion>
right above j3
<neggles>
interesting
<neggles>
i am assuming the... 3.5MM? jack on the back panel in the pic on svanheule's site is not stock
<aiyion>
I'll look for an usb cable for my backup tty -.-'
<neggles>
heh
<neggles>
highly recommend picking up a handful of the things from aliexpress or wherever, they're like $2-4 depending
<neggles>
I have about fifteen or so of various chipsets floating around just in case they die
<neggles>
...or get lost
<neggles>
adding a headphone jack for UART access is pretty clever actually.
<dwfreed>
yeah, it is
<dwfreed>
TRS serial connector
<neggles>
yah
<neggles>
excuse me while i go buy a bag of of panel-mount TRS connectors...
<neggles>
:P
<dwfreed>
hah, love it
<neggles>
i've gone and permanently installed an esp8266 wifi web terminal inside a few things
<neggles>
mostly ones that absolutely suck to disassemble
<neggles>
but this is a much better idea :P
<dwfreed>
portable wifi web terminal that connects to your TRS jack, so you're not tethered to the device
<Habbie>
i see talk of openwrt-22.03, but no branch yet, is that correct?
<aiyion>
PaulFertser: Mhm. Just ordered a new ch341a after I burned the last one on gpio3. Will test tomorrow...
<aiyion>
Shouldn't it be 10.90.90.91/8 matching the device?
<PaulFertser>
aiyion: instructions like I pasted them in the commit message work. I do not remember device's IP but it was in same /24 subnet and distinct from 10.90.90.91
<svanheule>
aiyion_: so on the DGS-1210-10 F1, *J8* is the 4-pin header that connects to the SoC's uart? And J3 is then the 5-pin header next to it?
<grift>
so i guess theres two scenario's then. either cgi-io uploads the firmware image to /tmp (and maybe you can optionally specify an alternate location to upload the file to), and then cgi-io runs sysupgrade , which calls that script
<svanheule>
aiyion_: if you want, you can register on the wiki to correct any information you find to be wrong (and destroying you hardware)
<grift>
or you upload the firmware manually and then either run sysupgrade manually or just run the validate_firmware_image $IMAGE manually
<svanheule>
aiyion_: if you connected to J9 or J10, those are in the PoE power domain, so that could fry some things if you're not careful
<neggles>
svanheule: I see you've fixed the typo :D
<svanheule>
neggles: apparently it was _my_ typo >_>
<neggles>
you got it right in the first section :P
<neggles>
it looks like it's possible to drop a MAX232-family chip in the U17 footprint and add a 'proper' cisco RJ45 console socket to the front, too
<neggles>
damn shame they didn't do that from factory...
<svanheule>
neggles: wait, it wasn't my typo! it was J3 in the original version, then I copied that to the pin-out section. Later PaulFertser corrected it in the overview to J8; but the J8 marking isn't visible from the picture :-/
<neggles>
it is indeed not
<svanheule>
neggles: have you seen my JTAG mods? :-)
<neggles>
and it *looks* like the populated header is J3 from the photo, but it's not
<neggles>
not sure how useful JTAG on the realtek switches will be without BSDL but maybe urjtag finds something it can use?
<svanheule>
the JTAG chain has two devices, one of them the MIPS CPU
<svanheule>
I can halt that one, and dump memory with OpenOCD
<neggles>
nice!
<neggles>
I have a firebox T20 here (LS1023A) I soldered an M.2 socket onto earlier today, it has everything wired up for SATA except the actual socket, and had a pre-populated cortex-debug header
<neggles>
i don't know if that works, though, since they didn't bother to turn on secure boot, so I just binpatched my way around their password check. one little `cbz` changed to `cbnz`...
<svanheule>
an M.2 socket!? do you have reflow equipment?
<neggles>
yup
<svanheule>
neat
<neggles>
858D hot air pencil
<neggles>
they're like 50-60USD these days I think?
<neggles>
...then there's the $800 JBC soldering iron but we don't talk about that
<svanheule>
:P
<neggles>
though
<svanheule>
hey, good equipment can be well worth its money
<neggles>
oh yeah i bought it about 8 years ago and it was worth every cent
<neggles>
(the cheapo android tablet is optional, thankfully)
dedeckeh has quit [Remote host closed the connection]
csrf has quit [Ping timeout: 480 seconds]
<robimarko_>
svanheule: DGS1210-28P also has unpopulated JTAG
csrf has joined #openwrt-devel
<svanheule>
robimarko_: I also noticed it on the 10P when I was looking at the pictures. I've added tags for the DGS-1210-10P, -16, -28, and -28P on the wiki
goliath has joined #openwrt-devel
Tapper has quit [Ping timeout: 480 seconds]
pepe2k has quit [Quit: Leaving]
<robimarko_>
Whole series pretty much shares the same PCB
<robimarko_>
neggles: Yeah, they skimped on a proper console
<robimarko_>
There is even a footprint for the RJ45
<neggles>
yup
<neggles>
and all the passives around the RS-232 level shifter
<neggles>
literally missing the socket and chip
<robimarko_>
Well, you know thats 1 USD off the BOM
<svanheule>
We should start making lists with upgrade kits for our favourite Realtek switches :P
ephemer0l has joined #openwrt-devel
danitool has joined #openwrt-devel
srslypascal has quit [Ping timeout: 480 seconds]
<robimarko_>
I wouldnt be surprised if there is a market for that
<robimarko_>
I still cannot figure out DGS-1210-28P and the I2C GPIO bus for the fan controller
<robimarko_>
SCL pin toggles fine manually but if used in I2C-GPIO it just floats basically
csrf has quit [Ping timeout: 480 seconds]
srslypascal has joined #openwrt-devel
<svanheule>
robimarko_: does it also float if you manually change it to input? it sounds like the pull-up is missing, but I have the feeling we've discussed this before...
<robimarko_>
Yeah, we discussed it a while ago
Tapper has quit [Remote host closed the connection]
Tapper has joined #openwrt-devel
<robimarko_>
I think that there was 4.7k pull-up
<robimarko_>
Need to look into it again soon
<hurricos>
aiyion: neggles: I'm going to need photos of your T20-W's :^)
<hurricos>
esp. 'program the nuvoton chip' is it a superio or somesuch?
<hurricos>
never mind, two different boards here. Nuvoton MCU for controlling broadcom crap
arjun has quit [Quit: Page closed]
csrf has joined #openwrt-devel
<hurricos>
Has anyone actually received an order from AsiaRF?
<hurricos>
I'm unable to call the number listed on the order, haven't heard back from their sales, and (not having created an account) have no way to look up the status of my order.
lemmi has quit [Remote host closed the connection]
<tmn505>
hurricos: last Year in October I mad an order. It took more than three weeks, since confirmation from AsiaRF, for FedEx to announce the dispatch. Then it took three weeks till delivery.
lemmi has joined #openwrt-devel
mattytap_ has joined #openwrt-devel
mattytap has quit [Read error: No route to host]
mattytap__ has joined #openwrt-devel
minimal has joined #openwrt-devel
mattytap_ has quit [Ping timeout: 480 seconds]
<hurricos>
tmn505: That's comforting, thank you. It's been just over 3 weeks since the initial order and I've been unable to reach them, so we'll see what comes.
<aiyion_>
svanheule: I was in the poe domain and its definitely possible I was not careful enough. But for F1 J8 is the SoC Uart, yes.
T-Bone has quit [Ping timeout: 480 seconds]
indy has quit [Ping timeout: 480 seconds]
<aiyion_>
J3 had more than four unpopulated pins, and was directly next to / below J8.
rua has quit [Ping timeout: 480 seconds]
<aiyion_>
robimarko_ its not only a footprint on the board; the 10P even has a hole for the rj45jack in the metal casing in the front which is just blocked by thin plastic.
<neggles>
hurricos: if you do create an account it should auto-link to view status; they changed their webstore recently… I haven’t received anything from them myself but I know someone who has
<neggles>
aiyion: hurricos got mixed up over what boards we were working with :P
<neggles>
hurricos: fwiw my T20 is not a T20W, the wifi part of the board is unpopulated (but I can take you pics anyway)
<neggles>
i should have a ramboot image that works now