ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<medfly>
drivers/gpu/drm/amd/display/dc/dcn{31,32,35,301,314,321}/Makefile have an interesting copyright notice probably forgotten before an initial import
<DemiMarie>
FL4SHK: GPUs are SIMT for a reason, MIMD will have too much overhead for performance.
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<FL4SHK[m]>
<DemiMarie> "FL4SHK: GPUs are SIMT for a..." <- can you tell me why?
<FL4SHK[m]>
MIMD just means all the cores have separate instruction streams
<FL4SHK[m]>
though separate caches...
<FL4SHK[m]>
maybe it's the bus accesses?
<FL4SHK[m]>
or the cache coherence, but I'm not sure how you avoid cache coherence with SIMT
<FL4SHK[m]>
oh
<FL4SHK[m]>
Wait I think I get it
<FL4SHK[m]>
though
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<FL4SHK[m]>
wait no you can't necessarily avoid data cache coherence if you have two cores using the same address
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<FL4SHK[m]>
guess it might have to do with atomics
<FL4SHK[m]>
though if you have multiple threads, you need those too
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<airlied>
agd5f: might want to fix the above ^
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<DemiMarie>
<FL4SHK[m]> "MIMD just means all the cores..." <- That’s the overhead. GPUs use SIMT to amortize the overhead of instruction decoders and the like.
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<DemiMarie>
Without SIMT, most of the die area would be spent on control logic, rather than on compute. Nowadays, SIMT is a large part of what makes a GPU a GPU — there are compute GPUs that don’t even have the ability to render graphics.
<einecardiograph>
they do not amortize the overhead of decoders though multiple cores remark mimd vs simd sounds right VLIW is something similar to mimd.
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<einecardiograph>
i see a minor disambiguation between decoders and encoders i deal with and the decoders on hw too btw. as well as i see a trouble of doing my encoders without loops and bitshifts, it's not possible, however dma packets can bitshift well or unaligned access , but in the same subject if you amortized the cost of opencl decoders you would lose the cores, gpu is very complex hardware and
<einecardiograph>
nowdays they use most often so called programmable shading hw which is not fixed anymore but most oftenly unified.
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<FL4SHK[m]>
question: do GPUs include virtual memory?
<stsquad>
I'm trying to decode some acronyms, any idea what a shmem virgl GBM FB BO is and why they get allocated for KMS rendering and not under a GUI toolkit?
<karolherbst>
FL4SHK[m]: yes
<FL4SHK[m]>
hmm
<FL4SHK[m]>
how does that work?
<FL4SHK[m]>
I'll have to include virtual memory in my design
<karolherbst>
applications can allocate a VMA context of whatever form, and then commands submitted by applications have a VM attached
<FL4SHK[m]>
what's VMA? virtual memory address?
<karolherbst>
ehh I meant VM
<FL4SHK[m]>
gotcha
<FL4SHK[m]>
I'll have to develop this machine further
<karolherbst>
command buffers can contain things like "copy from this VMA to this VMA"
<FL4SHK[m]>
what's VMA?
<karolherbst>
an address in this case
<FL4SHK[m]>
gotcha, so it's a virtual address?
<karolherbst>
yeah
<karolherbst>
shaders also operate on virtual addresses for things like ssbos or global memory in compute APIs
<FL4SHK[m]>
I see
<FL4SHK[m]>
my plan is to make a partially MIMD GPU, just to speed up compute tasks
<karolherbst>
yeah.. ignoring 3D for now isn't the worst idea
<FL4SHK[m]>
... but with each core having SIMD operations
<FL4SHK[m]>
well 3D is something I think I can handle
<karolherbst>
the question is mainly how much of 3D do you want to do in hardware and how much in software
<FL4SHK[m]>
I wrote a software rasterizer to learn about am the graphics pipeline
<FL4SHK[m]>
well
<FL4SHK[m]>
I heard that rasterization is often done in hardware
<FL4SHK[m]>
the actually drawing triangles stuff
<FL4SHK[m]>
and clipping I think could be done in hardware
<FL4SHK[m]>
Could be wise to do those two in their own pipelines
<FL4SHK[m]>
but I'm not sure how fast I can make that
<FL4SHK[m]>
to me it makes sense to include multiple pipelines for rendering
<tzimmermann>
vsyrjala, ack
<vsyrjala>
tzimmermann: thanks
<FL4SHK[m]>
pipelines here being hardware pipelines
<FL4SHK[m]>
not talking about the graphics pipeline in this case
<FL4SHK[m]>
perhaps a tiled renderer could be wise for what I'm doing
<FL4SHK[m]>
I hope that answers your question karolherbst:
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<MrCooper>
Company: one issue with using EGL on X instead of GLX is that there's no functionality corresponding to GLX_OML_sync_control & GLX_INTEL_swap_event, which makes frame scheduling hard
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<Company>
MrCooper: interestingly, nobody has complained about that yet (and afaik nvidia has been using EGL over GLX for years)
<Company>
but good that you amde me aware of that difference
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<jadahl>
Company: NVIDIA doesn't support GLX_INTEL_swap_event
<Company>
true, it could be that nvidia is just worse no matter what you do
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<DemiMarie>
FL4SHK: do you plan to make your GPU something that would have decent performance if implemented on an ASIC?
<FL4SHK[m]>
Demi: I have no way to get an ASIC made, so probably not?
<FL4SHK[m]>
ASICs are expensive
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<DemiMarie>
FL4SHK: There are actually ways to do that (on old processes) via various programs.
<FL4SHK[m]>
really?
<FL4SHK[m]>
I've heard of Google Skywater
<DemiMarie>
Yes
<FL4SHK[m]>
Hmm
<DemiMarie>
But an FPGA is still good for development.
<DemiMarie>
FYI, GPUs used to be SIMD and later moved to an SIMT model.
<FL4SHK[m]>
right
<DemiMarie>
I am more interested in whether your design is overall high performance and would be within an order of magnitude of the performance of modern hardware if built on the same process.
<FL4SHK[m]>
Honestly I don't know
<FL4SHK[m]>
if it were, that would be nice
<DemiMarie>
Also, SIMT is not an implementation detail anymore. It is explicitly exposed in APIs.
<FL4SHK[m]>
I see
<FL4SHK[m]>
I've done some CUDA development
<DemiMarie>
So you will need an SIMT architecture to support the latest features.
<FL4SHK[m]>
huh
<FL4SHK[m]>
that's... interesting
<FL4SHK[m]>
Not exactly what I wanted to hear
<DemiMarie>
Wave and subgroup ops are what you are looking for.
<DemiMarie>
I suggest implementing a Vulkan driver for your hardware before finalizing the hardware design.
<FL4SHK[m]>
I wanted to do that
<DemiMarie>
That will ensure you have all the needed features.
<FL4SHK[m]>
Also as long as I don't get an ASIC made I'm free to change the design
<DemiMarie>
Yup
<FL4SHK[m]>
I have never really done ASIC designs before
<FL4SHK[m]>
just FPGA dev
<FL4SHK[m]>
can you tell me more about wave and subgroup ops?
<FL4SHK[m]>
Like, what are they
<FL4SHK[m]>
I might be able to implement SIMT on my MIMD design, if I understand correctly
<FL4SHK[m]>
but still be better in some ways for general purpose compute
<FL4SHK[m]>
not sure this is the case
<jenatali>
Wave and subgroup ops are exposing the SIMT data as SIMD instead
<FL4SHK[m]>
I see
<FL4SHK[m]>
I'll study up
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<FL4SHK[m]>
Demi: can you give me some documentation I could read about this stuff?
<FL4SHK[m]>
or point me to it
<DemiMarie>
FL4SHK: I would look up the SPIR-V and Vulkan specs, along with the operations supported by the latest GLSL to SPIR-V translators.
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<FL4SHK[m]>
ah
<FL4SHK[m]>
thanks
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<retroassembling>
I do not have info to deliver left anymore, I am coding again as of now, cleaning my home lab and tomorrow i drop most of the oftc usernames there are many :)
<retroassembling>
i understand that i mixed up minuend and subtrahend meaning, but overall research is still entirely graduated, no more details
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<retroassembling>
also DemiMarie was talking about some mmu stuff, that i was not able to grasp, but soft-mmu can be exposed much the similar compacted form, as long as one allocates enough basically anything could be now done from sw.
<retroassembling>
I have so much programming to do, i figured i deal with rtlinux and rtoses as of now, to see if they spawn minimal amount of processes, zephyr does not well support x86
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<Mis012[m]>
what would "well support" mean, adding ACPI support to zephyr would be kinda insane, and the other staple of x86 designs is initializing stuff in uefi and then pretending to the OS that it doesn't need initialization, which in this case probably doesn't hurt too much?
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<Mis012[m]>
stsquad: shared memory virtual gl general buffer manager framebuffer buffer object probably, but virgl refers to OpenGL pass-through to a VM afaik
<retroassembling>
yes, indeed , i agree with this comment. There is native_posix and it was maximum to be able to offer to users.
<retroassembling>
i actually have 5 laptops and all of them are supported by coreboot for a coincidence, and i have one fitpc which also has some support.
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<retroassembling>
but i do not recommend random people to deal with synthesizing gpu hardware, it's the most complex commodity hw, i did spend nearly five years looking at miaow code namely cause my life sucked and i had nothing to do, but the results i came out with matched the comments in the mailing list with/by tom stellard. Only thing was that he commented this at year 2012, but my conclusions one
<retroassembling>
to one came in 2018 or something, so 6 years later, so under normal conditions this was waste of time but once again i was sanctioned in my country and had nothing other to do.
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<uis>
Can rendering be sped-up by binning groups of triangles in engine?
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<karolherbst>
uis: you mean like glDrawElements?
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