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<calebccff>
sima: lumag: personally my main concern is with the single upstream user for fastrpc (that I'm aware of) -- it's an essential part of the fragile tech stack required to access any of the sensors on Qualcomm phones... And it feels like any changes to the fastrpc driver could break this
<lumag>
calebccff, but isn't libssc a QMI-only library? In other words, does it depend on the actual fastrpc implementation?
<calebccff>
lumag: yeah it's QMI only, it's just that no sensors show up if you don't first initialize the DSP over fastrpc
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<nuggetpeer>
so execution is the most interesting, so you add a value to the hash in the minuend, and perform subtraction to access the value through index, but it's swizzled for dependencies so you presubtract the constant once from mother cell then remove distance/length from all do the same with daughter cell, then remove all other constants, and in practice the access value should fictively ripple
<nuggetpeer>
through the scaffold over the pc's, in the dependency pc the index and offset are switched so that one of them that alternates over one pc is missing, all other logic is easier. But the value at some certain pc's intermediate result to for instance commit io write is where it gets more interesting now you want to remove the pc's that are not needed forward from poi. so you index a data
<nuggetpeer>
bank and access multiple banks with indexes and remove those pc's, i gotta say technically i have the framework ready with all modules, but i am programming that solution til the end of the year, i have already said that in such form on irc it is my last, cause i do not like what you do, the abstract over the p2p dma is a subject that concerns me little, but i saw that airlied pointed out
<nuggetpeer>
some nvidia employee work of the engine that does peer to peer dma , i have my own view about this issue, but i do not dig into it anymore, but for starters someone could test it and try to bisect for upstream inclusion and hopefully we can later implement the logic that computes on dma chipset add and sub is needed, i know how to do that now based of cornell rpi2400 examples.
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<FL4SHK[m]>
There appears to be quite a bit of AI spam posts in this channel...
<zamundaaa[m]>
FL4SHK: it's not AI, that's a person
<FL4SHK[m]>
oh
<FL4SHK[m]>
sorry
<ccr>
as amazing as it may sound, but yes. and he keeps on using vpns, etc. to avoid bans.
<FL4SHK[m]>
I see
<ccr>
been going on for many, many years
<FL4SHK[m]>
Huh
<FL4SHK[m]>
ten years?
<FL4SHK[m]>
twenty?
<ccr>
probably close to ten
<FL4SHK[m]>
ah
<FL4SHK[m]>
the messages read like AI spam to me anyway
<MrCooper>
most definitely more than ten
<MrCooper>
can't really remember when he wasn't around yet
<FL4SHK[m]>
I'm not sure what he's trying to achieve
<ccr>
mental problems
<FL4SHK[m]>
ah
<ccr>
has some kind of "beef" with FLOSS people, this is not the only channel he frequents
<MrCooper>
he's under the illusion that he knows better than all of us how to do what we do
<MrCooper>
*delusion
<FL4SHK[m]>
I have some mental stuff myself, though I'm not sure they're promoting... I was diagnosed with Asperger's as a kid, ADHD, and some other stuff
<FL4SHK[m]>
though I'm not sure they're problems*
<FL4SHK[m]>
they don't really cause much issue for me
<ccr>
it's best just to ignore him and not engage directly, someone will usually ban his current account(s) eventually. it is practically impossible to get rid of him tho, due to how he evades using vpns or tor or whatever.
<FL4SHK[m]>
right
<FL4SHK[m]>
I haven't used Tor in a long time, maybe ten years, and I barely used it at that
<FL4SHK[m]>
I've been doing computer stuff for such a long time... it's both a hobby and my job
<FL4SHK[m]>
I am considering using the simple pipeline implementation of my CPU as a programmable GPU
<FL4SHK[m]>
I'm almost done with the first version of the CPU
<FL4SHK[m]>
I'll just have to support multiple cores
<FL4SHK[m]>
But hopefully I can fit a bunch of these in my FPGA
<FL4SHK[m]>
not sure how fast they'll run but I think a MIMD GPU could be cool
<FL4SHK[m]>
... though maybe I'd benefit from upgrading to a 64-bit instruction set
<FL4SHK[m]>
it's 32-bit right now
<FL4SHK[m]>
and only integer instructions are defined right now, but I'll add floating point instructions if I decide to go through with this...
<FL4SHK[m]>
there is some support for 64-bit integer ops
<FL4SHK[m]>
for divides and full products (though the full products produce 64-bit ops)
<FL4SHK[m]>
*produce 64-bit values
<FL4SHK[m]>
instruction set so far is at `flare32_cpu` on my Github at the "fl4shk" account
<FL4SHK[m]>
and so is what I have so far for the implementation of the FPGA code
<FL4SHK[m]>
I also wrote a GCC backend targeting the CPU
<FL4SHK[m]>
but it's not complete
<FL4SHK[m]>
it can compile C++ code that doesn't use the standard library
<FL4SHK[m]>
still have to port picolibc
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<freedomofword>
intelligence can not be measured through indications or comparison to human excrements like you, excrements and fecalists is what you are, it is insulting to compare intelligence or measure through such references. Human excrements like you get integrated with content of canalisation in the concentration camp which is your destiny on this planet in human history, for a fact there is
<freedomofword>
absolutely nothing human excrements can be good at. If you look at how MrPooper or DemiMarie or any other retarded jew like airlied shows out in the world, it's unrelated to intelligence in grandest way. MrPooper is with 2cm thick oculars and with smaller brain than a reptilian or say rene rebe Ermine jewsih looks, you are entire freaks and extremely stupid human garnage and i say they
<freedomofword>
integrate you with content of canalisation in the concentration camps.
<Ermine>
dwfreed: requesting banhammer
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