ChanServ changed the topic of #dri-devel to: <ajax> nothing involved with X should ever be unable to find a bar
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<DemiMarie> How big of a hit do Intel and AMD take when rendering to linear buffers?
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<mareko> DemiMarie: I'm guessing -75%
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<DemiMarie> mareko: what about with a copy to linear and back?
<DemiMarie> I’m finding validating nonlinear buffers to be a nightmare.
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<mareko> DemiMarie: if you use the gfx pipeline, -75% regardless of how you do it
<DemiMarie> mareko: what about if I use a copy engine?
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<mareko> DemiMarie: -90% if the copy engine is 10x slower than VRAM (the copy engine is meant to be for copies over PCIe, which is ~20x slower than VRAM)
<DemiMarie> mareko: dang it!
<mareko> DemiMarie: if you use compute and 64x1 workgroups (linear access pattern), it should be fast, or glBlitFramebuffer/glCopyImageSubData if the driver implements it that way
<DemiMarie> Is fuzzing compositors and UMDs the best option?
<DemiMarie> mareko: Nice!
<DemiMarie> The problem I am dealing with is making sure that the compositor won’t read out of bounds when passed maliciously crafted buffers.
<DemiMarie> For linear buffers this is trivial, except for alignment. For nonlinear buffers it seems that the best I can do is hardware-in-the-loop fuzzing of thousands of lines of Mesa code.
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<DemiMarie> Does robustImageAccess2 typically check against the image size or dimensions? If it checks against the image size, then my concern is completely mitigated.
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<mareko> DemiMarie: it checks against the result of imageSize() in GLSL
<mareko> there is never any out-of-bounds access if you don't use pointers in shaders
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<MrCooper> DemiMarie: buffer access is always bounded within height * stride, even with tiling; though note that the height needs to be aligned to a tile boundary
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<MrCooper> zamundaaa[m]: I'd have to see the code, FWIW adjusting the source & destination coordinates of the blit works in xf86-video-amdgpu/ati though
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<emersion> maybe glCopyTexSubImage would help
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<zamundaaa[m]> MrCooper: hmm, this code binds the buffer from the iGPU as a texture and uses that to render to the buffer on the dGPU. I haven't actually tried blitting
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<MrCooper> zamundaaa[m]: FWIW, "blits" are really textured quads with glamor in xserver
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<DemiMarie> MrCooper: if a tile is X bytes, are offset and stride required to be a multiple of X bytes?
<DemiMarie> MrCooper: also, if I have a bunch of questions on modifiers, what is the best time to ask them?
<MrCooper> the size of the buffer area which may be accessed is a multiple of the tile size, the stride not necessarily though
<MrCooper> as always on IRC, just ask anytime, don't expect an immediate answer though
<MrCooper> DemiMarie: the common definition of stride with tiling is a multiple of the tile width (>= the image width) multiplied by bytes per pixel
<DemiMarie> MrCooper: is there a way to get the tile width from a dmabuf?
<DemiMarie> MrCooper: can I assume that if client-provided stride is not an integer multiple of the bytes per pixel, the client is buggy?
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<DemiMarie> The reason I asked about time is that IRC doesn't have message history built in, and I wasn't sure if a question asked when people are offline would be seen later.
<DemiMarie> Also, can I assume that if the format is subsampled, the width and height will be multiples of the subsampling ratio? That seems to be implied by the Vulkan valid usage requirements.
<MrCooper> DemiMarie: not that I know of, the tile width is part of the modifier definition
<DemiMarie> MrCooper: will the offset always be a multiple of it?
<MrCooper> don't think it necessarily has to be
<DemiMarie> Does that mean that for a given format and modifier, I can compute the minimum buffer size without knowing the hardware?
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<agd5f> modifiers only relay the layout, not alignment requirements
<DemiMarie> Is that because the alignment requirements are always computable from the modifier and format for a given hardware model and generation?
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<agd5f> Not sure about alignment requirements within a GPU vendor. I would assume they should be compatible, but modifiers don't require that as far as I know. In general alignment requirements tend to be complex so it was a hard problem to solve.
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<tarceri> py311-generator: FAIL code 1 (38.19=setup[5.43]+cmd[32.76] seconds)
<tarceri> Anyone know whats going on in these jobs with piglit?
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