14:34 <warpme> apritzel : what is stability of yours opi zero3? I finally got it working with all periph i need - but getting it fully booted is practically impossible for me: board - in majority attempts - randomly freezes during boot. I can't catch such hangs with xulong opios distro (archlinux based with their 6.1 kernel) - so it looks my issue isn't hw related. My other h618 box (vontar) works days without single issue with my software - so it

14:34 <warpme> looks like opi zero3 has something "unique"....

14:35 <apritzel> warpme: do you see random kernel oopses? Those typically point at not-quite-right DRAM parameters

14:35 <apritzel> what is your U-Boot/DRAM setup anyway?

14:36 <apritzel> and are the occasions when it works fine? Or does it always hang, just sometimes takes longer?

14:44 <warpme> first i tried u-boot you hinted me yesterday (thx). with it board hangs 3..5 times on 10 attempts. Hang is before uboot proper (tpl). So next i dumped uboot from opios (it is based on 2023.07.01). With this uboot seems reliable - but following kernel boots are the same unstable...

14:48 <warpme> btw: i said: with opios uboot - boot seems reliable. Well - it is only when ram is sized correctly (half boots hangs due wrongly ram sizing at 8G)

14:51 <apritzel> warpme: thanks, that's good info. In the past the vendor provided firmware had at least a stable DRAM setup, seems like this is not really true anymore :-(

14:52 <apritzel> and I haven't done any stability testing at all, I was just happy to get it booted via FEL with an initrd, so I could test the DT

14:52 <apritzel> but I didn't see any hangs during my (admittedly few) attempts

15:01 <apritzel> warpme: oh, just wondering: do you have an AXP313a patch for U-Boot (the SPL, really)?

15:01 <apritzel> that's needed because I think the default AXP voltage for DCDC3 is not the expected 1.1V for LPDDR4

15:03 <warpme> generally (i mean uboot im using for other h313/h616/h618 boards) - yes. for zero3 im using bin dumped from opios sd card (or from url with u-boot.bin yoy provided me yestrday)

15:05 <apritzel> ah, I see. The reset value for the respective DCDC3 register is 0x28, which is something like 1.28V, if I didn't mess this up

15:06 <apritzel> I think this might be fine for the operation, but might produce glitches if Linux then corrects this voltage down to 1.1V, once the PMIC driver initialises

15:12 <apritzel> warpme: or it might be much more mundane because I mixed up the limits on DCDC1 and DCDC2 in the DT ;-)

15:13 <apritzel> but it's so much easier to complain on other people's patches about those things, ask DarkNeutrino ;-)

15:15 <DarkNeutrino> ?

15:16 <apritzel> because I pointed out the limits in your patch, but actually got that wrong in mine ;-)

15:17 <DarkNeutrino> Ah right :)

15:19 <DarkNeutrino> Btw apritzel the BTT u-boot has axp313a code. Its mangled and not really nice but its there :)

15:19 <apritzel> yeah, there are several patches to the same effect, including one I quickly cooked up myself on the weekend

15:20 <DarkNeutrino> And mainly it works. I just run downstream u-boot from BTT with kernel mainline

15:20 <apritzel> but as you said, it's not really nice, and I am in the middle of a rework of this hideous AXP setup code

15:20 <DarkNeutrino> Cause lets be honest. I need something stable as base to know that hey things work before i take hammer to the foundation lol

15:22 <apritzel> well, in the past the board-vendor provided firmware was just so bad that it wasn't really an option.

15:23 <apritzel> I think it's just with the H616 that we see more mainline firmware adoption by the vendors, even though they are lagging behind by two years

15:26 <apritzel> and the whole DRAM situation by the vendors doesn't seem to be ideal either, given the three images provided by Orange Pi for the same board (to cover different DRAM sizes)