06:24 <ity> Hi! Anyone has info about the D1 BROM ?

09:40 <apritzel> ity: there is a dump in the sun20i directory in here: https://github.com/smaeul/sunxi-blobs/tree/master

09:40 <apritzel> not too much info, but some symbols, at least

15:43 <jernej> apritzel: some dram improvements: https://github.com/jernejsk/u-boot/commits/a523/

15:43 <jernej> comments welcome :)

17:13 <apritzel> jernej: so PHY write training is not really working, or is not tested, that's why you remove it?

17:14 <jernej> it is just copy from h616, which don't work here

17:28 <apritzel> looks quite good after a first glance, really like it

18:09 <eliasbakken> Has anyone played around with the CPUS on the T527? It's not well documented, but it seems there is a OR1000-style CPU buried in there. I've tried poking around the reset register for the CPUS from a booted board, but it leads to an instant freeze.

20:35 <apritzel> eliasbakken: jernej discovered the ARISC before, but not sure he got something running on it

20:47 <jernej> no, nothing yet

21:59 <eliasbakken> Right, so am I right in assuming that there is an ARISC present? The user manual seems to place the ARSIC and the RISCV both in the CPUS domain, so I'm guessing they might share the same peripheral bus or something. There is also an SCP.bin file in the Orange Pi 4A Debian distro, so it seems to be loaded. Where would the code to do an AR100 reset be located? Is that in u-boot?

22:32 <loki666> apritzel: I'm having a similar issue with GPU (G31) as I had with the CPU: unstable when running a dynamic freq governor. It seems pretty stable when running powersave or perf, but panfros does some oops when running simple_ondemand gov

22:32 <loki666> could it be that devfreq doesn't honor the ramp delay ?

22:35 <loki666> mmmh, no... on a second thought it can't be that as all opp use the same voltage...

22:51 <apritzel> also devfreq would just use the regulator framework, which would handle the ramp delay

22:54 <apritzel> loki666: I guess we need some reparenting and re-locking as done for the CPU PLL, see the end of sun50i_h616_ccu_probe() in the clock driver

22:58 <macromorgan> has there been any movement on the DE33 patches? https://lore.kernel.org/linux-sunxi/20240929091107.838023-1-ryan@testtoast.com/

22:59 <apritzel> no, but any reviews are welcome ;-)

23:00 <apritzel> eliasbakken: we are pretty sure that there is an ARISC, since there is OpenRISC code in the BSP firmware

23:01 <apritzel> eliasbakken: the code to release the ARISC from reset would probably be in TF-A, at least I haven't seen anything in Syterkit

23:03 <apritzel> loki666: the manual doesn't even mention frequency scaling for GPU_PLL (in contrast to the H6, for instance), so we really need to reparent the GPU clock over frequency changes

23:10 <macromorgan> I can give a belated tested by I suppose... I can try to review it but considering I'm 100% self taught it might be a review of dubious quality

23:18 <apritzel> I don't think there is anyone professionally educated for display engine review anywhere ;-)

23:25 <macromorgan> fair enough

23:59 <loki666> DE33 works fine