marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | "Does XXX work yet?": https://alx.sh/fs | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-alt #asahi-stream #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
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<mmuller> is it possible to instal asahi on an M2 mini?
<mmuller> tried the main install and the new fedora remix
<mmuller> both say my device is not supported yet
<mmuller> the web site says i need to enable expert mode, but i'm not given that option in the installer
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<marcan> it's not supported yet
<marcan> if it says it's not supported yet it's not supported yet
<marcan> where does it say you need to enable expert mode?
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<sleepntsheep> Hello
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<tpw_rules> do common desktop distros (and macos for that matter) run a lot of stuff in thumb mode?
<ChaosPrincess> they run exactly zero code in thumb mode as it does not exist in 64 bit arm
<tpw_rules> ah, easy answer. thanks
<tpw_rules> are 64 bit arm instructions always 4 byte aligned?
<tpw_rules> so says wikipedia
<ChaosPrincess> iirc yes
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<lena6> as far as i know, one of the big speedups that arm (and other architectures that work this way) is from not having to deal with variable sized instructions
<lena6> afaik modern x86 CPUs have 4 "instruction parsers" (are they called like that?), while M1/M2 processors have 8, which is a big contributing factor to their out-of-order-ness in instruction execution, and all of this is possible efficiently because parsing fixed size instructions is much easier and faster
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<tpw_rules> yes, but one of the points of thumb is it relaxes alignment to 2 bytes and has 2 byte wide instructions. i wondered if they left those sorts of instructions in armv8
<tpw_rules> and just ditched the mode
<lena6> they got rid of Jazelle too
<sorear> armv8 has a ton of instructions with two destinations, largely approaching the "common code needs 2 bytes per elementary operation" problem from the other direction
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<maz> lena6: amusingly, variable length instructions *are* part arm64 in the form of the SVE move prefix and the memory copy instructions (the latter always come in group of 3 instructions -- 12 bytes).
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<lena6> i don't know that much about the aarch64 ABI, but yeah, doing this kind of grouping would make sense
<lena6> actually though, x86 is such a mess
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<heksadecimal> hi
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<nightstrike> wifi on an M2 MBP is listed as TBA, and ethernet is '-'. Does that imply that there is no networking support currently? Or are there workarounds?
<tpw_rules> i mean - is probably because there is no built in ethernet
<tpw_rules> if usb works there should be no problems with a usb-ethernet or usb-wifi adapter
<nightstrike> ok, yeah I have a Dell dongle that I could try
<nightstrike> Assuming it hasn't broken after tons of work travel and kicking around the airport
<nightstrike> how different is the wifi hardware between M2 and M2 max/pro/ultra?
<nightstrike> I'm kinda surprised there's any difference at all
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