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<apritzel>
jernej: so my "ISA pingpong and then back to FEL" snippet works on H616, but not on A523
<apritzel>
I suspect it's the GICv3: the BROM enables the system register interface, so ICC_SRE is 1. But bit 0 resets to 0, and since this ICC_SRE is a system register itself, it would be affected by an RMR
<apritzel>
(in contrast to the MMIO programmable GICv2, which keeps it state of a core reset)
<apritzel>
I tried to set this bit to 1, but it didn't change anything. There is also ICC_MSRE, which must be programmed from monitor mode, and which controls the ability to change ICC_SRE
<apritzel>
so I tried to switch to monitor mode, set the bit, switch back to SVC, then program ICC_SRE, but it still hangs
<apritzel>
so either there is something wrong in my switching code, or there are more GICv3 sysregs to save
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<jernej>
apritzel: great find! Is GIC state important due to USB? GIC is way over my head, so I'll leave this to you.
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<BroderTuck>
'hwclock -r' no longer times out after adding clk_ignore_unused to the kernel command line.
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<BroderTuck>
and from the botlog I posted the other day: "[ 2.286560] sun55i-a523-r-ccu 7010000.clock-controller: Powering off unused clock bus-r-rtc"
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<apritzel>
BroderTuck: that's odd, do you have <&r_ccu CLK_BUS_R_RTC> in your DT?
<BroderTuck>
I'm using $fdtcontroladdr, so it's *your* dt I'm using
<apritzel>
just checking, since you mentioned warpme's repo yesterday
<apritzel>
jernej: the BROM always used interrupts for the USB-OTG operation. It's just since it's the first AW SoC with a GICv3 that we see those problems
<jernej>
apritzel: makes sense
<jernej>
apritzel: since some parts of DRAM driver were not tested or not even written, I'm considering to put warnings and panic in those routines. Would that work for upstream?
<apritzel>
yes, absolutely. Maybe something that doesn't blow up the code size too much
<apritzel>
I made some changes to your code, btw: I think we should use A523 as the SoC name instead of T527, so I changed all those symbols
<apritzel>
and I dropped this T527_GEN: it really is an NCAT2 chip, so I used either CONFIG_SUNXI_GEN_NCAT2, or CONFIG_MACH_SUN55I_A523 where something didn't apply (for instance the SRAM address)
<jernej>
sure, there are some annoying differences, but in general, it works
<jernej>
I assume you have now more unified and cleaned U-Boot code which I can use from now on?
<apritzel>
the cleaned up part is what I pushed to my github, but I haven't spend much time on my SPL bits, which differ a bit from yours
<apritzel>
main difference is that I reused clock_sun50i_h6.c and cpu_sunxi_ncat2.h. The latter is good, but your clock code differs, and I need to see how it fits in the H6 file
<apritzel>
we don't need to setup everything there, for instance the secondary cluster PLL and probably also the DSU PLL don't need to be touched in the SPL
<jernej>
I agree, but at the beginning of working on new platform I didn't know how everything fits together
<jernej>
do you have any TF-A related code? if not, I can take a look at it.
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<apritzel>
jernej: totally see your point: it's probably easier to copy and hack that copy, so no worries about that
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<apritzel>
no, nothing TF-A related yet, already too much on my plate anyway and I cannot review and push my own patches, so appreciate any help here
<apritzel>
the R329 is also NCAT2 (UART address and so on), so some code could be shared, I guess
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<apritzel>
jernej: which board revision is your Avaota, and does it have eMMC? Mine is v1.3, and has no eMMC soldered
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<jernej>
apritzel: same, v1.3 without emmc
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<BroderTuck>
Something is screwy. In clk_summary, 7090000.rtc is listed under bus-r-cpucfg, not bus-r-rtc where I would expect it to be
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<apritzel>
jernej: finally! Should have tried the obvious register first: ICC_IGRPEN, to enable interrupts on the CPU interface level ;-)
<apritzel>
now to figure out some details, and how to integrate this into U-Boot ...
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<apritzel>
it's ICC_IGRPEN1, specifically, and we also need ICC_PMR
<jernej>
apritzel: nice! let me know when you push some code. I'm used to FEL very much :)
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<jernej>
apritzel: just #ifdef it and be done with it ;)
<apritzel>
yeah, somewhat, but I'd rather save and restore it than just forcing some value
<jernej>
btw, what are offsets 0x1d4 and 0x1d8 used for? It looks like regular hotplug with some extra settings?
<apritzel>
wasn't that some "super standby" feature or so?
<jernej>
ah, I forgot everything about it
<jernej>
could be
<apritzel>
don't remember any details as well, but there was something special about it ...
<jernej>
apritzel: your hack doesn't seem to work for me on avaota a1...
<jernej>
ah, applied it wrong, sorry
<jernej>
hm... still something wrong
<jernej>
apritzel: is it possible that some previous state helped you here?
<apritzel>
possible, as mentioned FEL is very unstable on my Avaota, so I reset it a few times. But for me it makes the difference between working and not-working
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<jernej>
apritzel: I guess I'll wait till you push your code. It's possible that there is some issue in my SPL too
<apritzel>
jernej: ifdef's are a bit tricky because of the PC relative addressing in the code. I have a neat solution for fel_utils.S (move fel_stash up), but am thinking about GICv3 auto detection for boot0.h
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